EP3C10M164C8N Altera, EP3C10M164C8N Datasheet - Page 345

• Manufacturer Part Number: EP3C10M164C8N
• Description: IC CYCLONE III FPGA 402MHZ BGA-164
• Manufacturer: Altera
• Series: Cyclone IIIr

Specifications of EP3C10M164C8N

• No. Of Logic Blocks: 645
• Family Type: Cyclone III
• No. Of I/o's: 106
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 106
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 164
• Package Type: MBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2: Cyclone III LS Device Data Sheet
Glossary
Table 2–39. Glossary (Part 2 of 5)
© December 2009
Letter
Q
R
P
PLL Block
R
Receiver Input
Waveform
RSKM (Receiver
input skew
margin)
L
Term
—
Altera Corporation
The following block diagram highlights the PLL specification parameters.
Receiver differential input discrete resistor (external to the Cyclone III LS device)
Receiver Input Waveform for LVDS and LVPECL Differential Standards
High-speed I/O Block: The total margin left after accounting for the sampling window and
TCCS. RSKM = (TUI – SW – TCCS) / 2
Core Clock
Key
Single-Ended Waveform
Differential Input Waveform
CLK
Reconfigurable in User Mode
V
CM
Switchover
V
f
ID
IN
N
f
INPFD
V
ID
Definitions
PFD
—
M
CP
Phase tap
LF
VCO
Cyclone III Device Handbook, Volume 2
f
VCO
V
p - n
Positive Channel (p) = V
Negative Channel (n) = V
Ground
ID
0 V
Counters
C0..C4
CLKOUT Pins
f
f
OUT _EXT
OUT
GCLK
IH
IL
2–27