IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 227

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Power On Self Test—IXB2850
B.1.13
B.1.14
B.1.15
January 2007
Document Number: 05-2443-006
I
The I
access EEPROM that stores SPI-4 static alignment and SRAM deskew settings. Because
EEPROM content is used to store information about memory size, only addresses from
0x80 are available for testing. The tests cases presented in the following table are
executed.
LED POST
The LED POST tests are automatic tests checking proper work of CPLD devices
responsible for controlling LEDs. The operator is responsible for visual verification of
LED operation. The tests cases presented in the following table are executed.
Media Access POST
The test performs MAC/Framer, PHY/Serdes, and register verification. The test cases
presented in the following table are performed for:
Test ID
00h
01h
02h
03h
04h
Test ID
00h
01h
02h
03h
04h
Test ID
00h
01h
02h
03h
04h
05h
06h
2
• MMC#1devices; not applicable to IXB2850 boards
• MMC#2 devices
• Baseboard devices
• FIC devices
C POST
2
C bus is a software-emulated bus that uses two GPIO lines. The bus is used to
Description
Write-check test
Page write
Current position read
Random read
Sequential read
Description
Walking 0/1 test for baseboard/NPM LEDs
Default state of MMC#1 LEDs; not applicable to IXB2850 boards
Walking 0/1 test for MMC#1 LEDs; not applicable to IXB2850 boards
Default state of MMC#2 LEDs
Walking 0/1 test for MMC#2 LEDs
Description
Registers default values test for MAC/Framer device
Registers write/read test for MAC/Framer device
Registers default values test for PHY/Serdes device
Registers write/read test for PHY/Serdes device
Registers default values test for MAC/Framer ports
Registers write/read test for MAC/Framer ports
Registers default values test for PHY/Serdes ports
Intel NetStructure
®
IXB2850 Packet Processing Boards
TPS
227