IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 32

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Figure 12.
3.4
Intel NetStructure
TPS
32
Frame format transmitted to
Baseboard IXF1104 or FIC
without HEADER
(removed by FORK FPGA)
Frame format
with HEADER
HEADER Format: 0x0000000000000000 - Frame to IXF1104
Start Of Packet
Header
Start of Packet
End of Packet
End Of Packet
...
...
0x0000000100000000 - Frame to FIC
®
Data packets transmitted between NP and baseboard IXF1104 or FIC
Quad Gigabit Ethernet Mezzanine Card
IXB2850 boards operate with the Quad Gigabit Ethernet Mezzanine Card. The form
factor of this board is equivalent to the PMC mezzanine card standard IEEE P1386.1
and the card supports Ethernet fiber as the physical media.
The Quad Gigabit Etherenet Mezzanine Card consists of two parts: the Media Mezzanine
Card (MMC), which is the main assembly and a Fiber Media Interface Card (MIC-F),
which provides the interfaces to the front panel of the board. See
“Quad Gigabit Ethernet Mezzanine Card Mechanical Specification” on page 162
more information.
Figure 13
shows that the access module consists of an IXF1104 Quad Gigabit Ethernet MAC and a
Marvell* Alaska Quad Gigabit Ethernet PHY.
The IXF1104 is a quad port 10/100/1000 Ethernet Media Access Controllers (MAC) that
provides for data transfer up to 4 Gbps. It also supports four independent 10/100/1000
Mbps full duplex PHYs which have three different interfaces: SerDes with GBIC support,
GMII and RGMII.
The 88E1041 Alaska Fiber Quad contains four independent Gigabit Ethernet
transceivers. Support of 1000BASE-BX for fiber Ethernet is provided through an
integrated 1.25 GHz Serializer/Deserializer (SERDES). The 88E1041 supports several
types of MAC interfaces: GMII, RGMII, TBI and RTBI.
The interface to the network processor is supported through a SPI3 media interface,
and the PHY interfaces are Serialized/Deserialized (SerDes) with GBIC support, Gigabit
Media Independent Interface (GMII) or Reduced GMII (RGMII) selected on a per-port
basis.
Transmit Direction
IXB2850 Packet Processing Boards
is a block diagram of the Quad Gigabit Ethernet Mezzanine Card. The figure
Baseboard
IXF1104
SPI-3/4 Bridge
Fork FPGA
FIC
Frame format received from
Baseboard IXF1104 or FIC
Frame format
with HEADER
(added by FORK FPGA)
HEADER Format: 0x0000000000000000 - Frame from IXF1104
Start Of Packet
Header
Start of Packet
End of Packet
End Of Packet
...
...
0x0000000100000000 - Frame from FIC
Baseboard
IXB2850—Hardware Overview
IXF1104
Document Number: 05-2443-006
Section 12.1.1,
SPI-3/4 Bridge
Fork FPGA
FIC
January 2007
for