IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 84

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

7.3
7.4
Intel NetStructure
TPS
84
®
When a PMC card, such as an Adjunct Processor card is detected, the NPU deasserts
the AP reset signal after PCI bus initialization. The AP starts execution of boot ROM (or
BIOS) code, while the boot ROM software on the NPU initializes execution of operating
software (diagnostics or Linux kernel with target image). When AP Power On Self Test
(POST) is completed, the AP initializes execution of its own run-time image.
Each processor runs its own specific software image independently. There is no built-in
operating system synchronization mechanism for bootstrapping the two processors or
system runtime support, that is, the operating system on each processor does not
synchronize with the other's control. This design assumes that the application running
on the system is to take full responsibility for any synchronizing system activities. The
application can build its own synchronization using a shared-memory facility provided
by the operating system (that is, the memory of the other processor can be accessed
through the PCI bus; the range of shared memory depends on the PCI configuration).
Board Management Controller Firmware Overview
The Board Management Controller (BMC) is the first board component to start
operating when power is provided to the board. The BMC is responsible for the
following:
The BMC firmware resides in the BMC local flash memory. See
Management Controller Firmware”
BMC local flash memory.
Network Processor Firmware Overview
The Network Processor (NP) firmware comprises:
The NPU firmware resides in onboard flash memory. See
Processor Firmware”
memory.
• Access to I
• IPMI support for communication with the Shelf Management Controller
• Power Management and Hot Swap support
• IPMI support for board CPUs (NPU and AP)
• Initial Loader
• Boot Monitor
• Diagnostics
• Linux* Support Package (LSP)
IXB2850 Packet Processing Boards
The BMC accesses ID EEPROMs and voltage/temperature sensors installed on the
baseboard and associated cards. It can read and write ID EEPROM contents.
(ShMC)
The ShMC obtains from the BMC information about the type of the board and all
extension cards as well as information about sensors installed on the board (such
as the sensor identifier, type, acceptable value range, and currently reported
value).
The NPU and AP can communicate with the BMC to obtain the FRU Information as
well as the board sensor readings and chassis slot number.
2
C devices
for details on the organization and content of the NPU local flash
for details on the organization and content of the
Chapter 9.0, “Network
IXB2850—Firmware Overview
Document Number: 05-2443-006
Chapter 8.0, “Board
January 2007