IXB28504XGBEFS Intel, IXB28504XGBEFS Datasheet - Page 235

• Manufacturer Part Number: IXB28504XGBEFS
• Manufacturer: Intel

Specifications of IXB28504XGBEFS

• Lead Free Status / Rohs Status: Compliant

Diagnostics—IXB2850
C.1.16
Figure 51.
January 2007
Document Number: 05-2443-006
The user can specify how many times test is performed (default is 1).
Media Traffic Tests
The test performs initialization of MAC/PHY for Gigabit Ethernet and starts the
microcode responsible for receiving and transmitting frames. During these tests, the
media interfaces are verified by two types of loopback; system and line loopback (see
Figure
checksum; after reception, the checksum is verified. This loopback may require an
external loopback connection. In the case of a line loopback, an external packet
generator is needed.
Media loopback test types
The following devices are tested during the Media POST:
Test ID
06h
07h
08h
09h
• SPI-3/4 Bridge and Fork FPGA
• Baseboard MAC and PHY
• FIC MAC
• Quad Gigabit Ethernet Mezzanine Card MAC and PHY
Line loopback types
51). During a system loopback test, the microengine sends frames with a
MAC
PHY
NPU
generator
External
traffic
Description
Registers default values test for PHY/Serdes ports
Registers write/read test for PHY/Serdes ports
Registers default values test for MIC devices
Registers write/read test for MIC devices
MAC line loopback
PHY li n e loopback
Line loopback
System loopback types
MAC
NPU
PHY
loopback
External
physical
Intel NetStructure
MAC system l o opback
PHY system loopback
System l o opback
®
IXB2850 Packet Processing Boards
TPS
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