PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 109

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
3.7.4
The Command/Indication channel carries real-time status information between the
SBCX-X and another device connected to the IOM-2 interface.
• One C/I channel (called C/I0) conveys the commands and indications between the
• A second C/I channel (called C/I1) can be used to convey real time status information
CIC Interrupt Logic
Figure 58
A CIC interrupt may originate
– from a change in received C/I channel 0 code (CIC0)
or
– from a change in received C/I channel 1 code (CIC 1).
Data Sheet
layer-1 and the C/I handler of the SBCX-X. It can be accessed by an external layer-2
device e.g. to control the layer-1 activation/deactivation procedures. C/I0 channel
access may be arbitrated via the TIC bus access protocol. In this case the arbitration
is done in IOM-2 channel 2 (see
The C/I0 channel is accessed via register CIR0 (in receive direction, layer-1 to layer-
2) and register CIX0 (in transmit direction, layer-2 to layer-1). The C/I0 code is four
bits long. A listing and explanation of the layer-1 C/I codes can be found in
Chapter
In the receive direction, the code from layer-1 is continuously monitored, with an
interrupt being generated anytime a change occurs (ISTA.CIC). A new code must be
found in two consecutive IOM-2 frames to be considered valid and to trigger a C/I code
change interrupt status (double last look criterion).
In the transmit direction, the code written in CIX0 is continuously transmitted in C/I0.
between the SBCX-X and various non-layer-1 peripheral devices e.g. PSB 2161
ARCOFI-BA. The C/I1 channel consists of four or six bits in each direction.The width
can be changed from 4bit to 6bit by setting bit CIX1.CICW.
In 4-bit mode 6-bits are written whereby the higher 2 bits must be set to “1” and 6-bits
are read whereby only the 4 LSBs are used for comparison and interrupt generation
(i.e. the higher two bits are ignored).
The C/I1 channel is accessed via registers CIR1 and CIX1. A change in the received
C/I1 code is indicated by an interrupt status without double last look criterion.
shows the CIC interrupt structure.
C/I Channel Handling
3.5.4.
Figure
109
40).
Description of Functional Blocks
PEB 3081
PEF 3081
2000-09-27