PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 66

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
3.5.1.3
Note: In the activated states (AI8, AI10 or AIL indication) the 2B+D channels are only
Data Sheet
Command
Activation Request with
priority class 8
Activation Request with
priority class 10
Activation Request Loop ARL
Deactivation Indication
Reset
Timing
Test mode SSP
Test mode SCP
Indication
Deactivation Request
Reset
Test Mode
Acknowledge
Slip Detected
Resynchronization
during level detect
transferred transparently to the S/T interface if one of the three “Activation
Request” commands is permanently issued.
C/I Codes (TE, LT-T)
Abbr. Code Remark
DR
RES
TMA
SLD
RSY
Abbr. Code Remark
AR8
AR10 1001 Activation requested by the SBCX-X,
DI
RES
TIM
SSP
SCP
0000 Deactivation request via S/T-interface if left
0001 Reset acknowledge
0010 Acknowledge for both SSP and SCP
0011
0100 Signal received, receiver not synchronous
1000 Activation requested by the SBCX-X,
1010 Activation requested for the internal or
1111 Deactivation Indication
0001 Reset of the layer-1 statemachine
0000 Layer-2 device requires clocks to be
0010 One AMI-coded pulse transmitted in each
0011 AMI-coded pulses transmitted continuously,
from F7/F8
D-channel priority set to 8 (see note)
D-channel priority set to 10 (see note)
external Loop A (see note).
For a non transparent internal loop bit
DIS_TX of register TR_CONF2 has to be set
to ’1’ additionally.
activated
frame, resulting in a frequency of the
fundamental mode of 2 kHz
resulting in a frequency of the fundamental
mode of 96 kHz
66
Description of Functional Blocks
PEB 3081
PEF 3081
2000-09-27