PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 35

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
logic resets this bit again automatically after 4 BCL clock cycles. The address range of
the registers which will be reset at each SRES bit is listed in
3.2.5
The SBCX-X provides one timer which can be used for various purposes. It provides two
modes
after expiration of the selected period, and a periodic timer interrupt, which means an
interrupt is generated continuously after every expiration of that period.
Table 6
Address
When the programmed period has expired an interrupt is generated and indicated in the
auxiliary interrupt status ISTA.AUX. The source of the interrupt can be read from
AUXI.TIN and masked in AUXM.
Figure 10
Data Sheet
65
H
(Table
Timer Modes
Register
TIMR
SBCX-X Timer
Timer Interrupt Status Registers
6), a count down timer interrupt, i.e. an interrupt is generated only once
TRAN
MASK
AUX
MOS
CIC
Interrupt
ST
Modes
Periodic
Count Down
TRAN
ISTA
AUX
MOS
CIC
ST
35
Period
1 ... 63 ms
1 ... 63 ms
AUXM
TIN
EAW
WOV
Description of Functional Blocks
Figure
AUXI
TIN
EAW
WOV
9.
PEB 3081
PEF 3081
2000-09-27