PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 151

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.3.2
XXX_
TSDPxy
Register
CDA_TSDP10
CDA_TSDP11
CDA_TSDP20
CDA_TSDP21
TR_TSDP_BC1
TR_TSDP_BC2
This register determines the time slots and the data ports on the IOM-2 interface for the
data channels ’xy’ of the functional units ’XXX’ which are Controller Data Access (CDA)
and Transceiver (TR). The position of B-channel data from the S-interface is
programmed in TR_TSDP_BC1 and TR_TSDP_BC2.
DPS ... Data Port Selection
0:The data channel xy of the functional unit XXX is output on DD.
The data channel xy of the functional unit XXX is input from DU.
1:The data channel xy of the functional unit XXX is output on DU.
The data channel xy of the functional unit XXX is input from DD.
Note: For the CDA (controller data access) data the input is determined by the
TSS ... Timeslot Selection
Selects one of 32 timeslots (0...31) on the IOM-2 interface for the data channels.
Note: The reset values for TR_TSDP_BC1/2 are depending on the mode selection
Data Sheet
CDA_CRx.SWAP bit. If SWAP = ’0’ the input for the CDAxy data is vice versa to
the output setting for CDAxy. If the SWAP = ’1’ the input from CDAx0 is vice versa
to the output setting of CDAx1 and the input from CDAx1 is vice versa to the output
setting of CDAx0. See controller data access description in
(MODE0/1) and channel selection (CH0-2).
7
XXX_TSDPxy - Time Slot and Data Port Selection for CHxy
DPS
Register
Address
44
45
46
47
4C
4D
0
H
H
H
H
H
H
0
Value after Reset
00
01
80
81
00
01
H
H
H
H
H
H
151
( = output on B1-DD)
( = output on B2-DD)
( = output on B1-DU)
( = output on B2-DU)
( = transceiver output on B1-DD), see note
( = transceiver output on B2-DD), see note
TSS
Detailed Register Description
0
Chapter
3.7.1.1.
PEB 3081
PEF 3081
2000-09-27
RD/WR
(44-4D)