PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 67

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
Data Sheet
Indication
Deactivation Request
from F6
Power up
Activation request
Activation request loop ARL
Illegal Code Violation
Activation indication
loop
Activation indication
with priority class 8
Activation indication
with priority class 10
Deactivation
confirmation
Abbr. Code Remark
DR6
PU
AR
CVR
AIL
AI8
AI10
DC
0101 Deactivation Request from state F6
0111 IOM-2 interface clocking is provided
1000 INFO 2 received
1010 Internal or external loop A closed
1011 Illegal code violation received. This function
1110 Internal or external loop A activated
1100 INFO 4 received,
1101 INFO 4 received,
1111 Clocks are disabled if CFS bit of register
has to be enabled by setting the EN_ICV bit of
register TR_CONF0.
D-channel priority is 8 or 9.
D-channel priority is 10 or 11.
MODE1 is set to ’1’, quiescent state
67
Description of Functional Blocks
PEB 3081
PEF 3081
2000-09-27