PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 51

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

PEB 3081
PEF 3081
Description of Functional Blocks
Preliminary
Protection Circuit for Receiver
Figure 25
illustrates the external circuitry used in combination with a symmetrical
receiver. Protection of symmetrical receivers is rather simple.
1:1
Note: up to 10 pF capacitors are optional for noise reduction
Figure 25
External Circuitry for Symmetrical Receivers
Between each receive line and the transformer a 10 k = resistor is used. This value is
split into two resistors: one between transformer and protection diodes for current limiting
during the 96 kHz test, and the second one between input pin and protection diodes to
limit the maximum input current of the chip.
With symmetrical receivers no difficulties regarding LCL measurements are observed;
compensation networks thus are obsolete.
In order to comply to the physical requirements of ITU-T recommendation I.430 and
considering the national requirements concerning overvoltage protection and
electromagnetic compatibility (EMC), the SBCX-X may need additional circuitry.
3.3.7
S/T Interface Delay Compensation (TE/LT-T mode)
The S/T transmitter is shifted by two S/T bits minus 7 oscillator periods (plus analog
delay plus delay of the external circuitry) with respect to the received frame. To
compensate additional delay introduced into the receive and transmit path by the
external circuit the delay of the transmit data can be reduced by another two oscillator
periods (2 x 130 ns). Therefore PDS of the TR_CONF2 register must be programmed to
’1’. This delay compensation might be necessary in order to comply with the "total phase
deviation input to output" requirement of ITU-T recommendation I.430 which specifies a
phase deviation in the range of – 7% to + 15% of a bit period.
Data Sheet
51
2000-09-27