PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 55

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
3.4
Figure 28
7.68 MHz clock signal (f
(8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous to the received S/T frames.
In LT modes these pins are input and in LT-T mode an 1536 kHz clock synchronous to
S is output at SCLK which can be used for DCL input.
The FSC signal is used to generate the pulse lengths of the different reset sources C/I
Code, EAW pin and Watchdog (see
Figure 28
Data Sheet
XTAL
7.68 MHz
shows the clock system of the SBCX-X. The oscillator is used to generate a
Clock Generation
Clock System of the SBCX-X
OSC
f
XTAL
XTAL
). In TE mode the DPLL generates the IOM-2 clocks FSC
DPLL
Chapter
Reset
Generation
SW Reset
C/I
EAW
Watchdog
55
3.2.4).
Description of Functional Blocks
FSC (TE mode)
DCL (TE mode)
BCL (TE mode)
SCLK (LT-T mode)
125 µs
125 µs
125 µs
125 µs
t
t
t
t
250 µs
250 µs
250 µs
250 µs
PEB 3081
PEF 3081
2000-09-27
3081_06