PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 141

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
LP_A ... Loop Analog
The setting of this bit corresponds to the C/I command ARL.
0: Analog loop is open
1: Analog loop is closed internally or externally according to the EXLP bit in the
TR_CONF0 register
For general information please refer to
4.1.11
Value after reset: 40
SQRR
For general information please refer to
MSYN ... Multiframe Synchronization State
0: The S/T receiver has not synchronized to the received F
1: The S/T receiver has synchronized to the received F
MFEN ... Multiframe Enable
Read-back of the MFEN bit of the SQXR register
SQR11-14 ... Received S Bits
Received S bits in frames 1, 6, 11 and 16 (TE mode)
received Q bits in frames 1, 6, 11 and 16 (NT mode).
Data Sheet
7
MSYN MFEN
SQRR1 - S/Q-Channel Receive Register 1
H
0
0
Chapter
Chapter
141
SQR11 SQR12 SQR13 SQR14
3.3.10.
3.3.2.
A
Detailed Register Description
and M bits
A
and M bits
0
PEB 3081
PEF 3081
2000-09-27
RD (35)