PEB3081FV14XP Lantiq, PEB3081FV14XP Datasheet - Page 158

• Manufacturer Part Number: PEB3081FV14XP
• Manufacturer: Lantiq

Specifications of PEB3081FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

Preliminary
4.3.10
Value after reset: 08
IOM_CR
SPU ... Software Power Up
0: The DU line is normally used for transmitting data
1: Setting this bit to ’1’ will pull the DU line to low. This will enforce connected layer 1
devices to deliver IOM-clocking.
After a subsequent ISTA.CIC-interrupt (C/I-code change) and reception of the C/I-code
”PU” (Power Up indication in TE-mode) the microcontroller writes an AR or TIM
command as C/I-code in the CIX0-register, resets the SPU bit and waits for the following
CIC-interrupt.
For general information please refer to
DIS_AW ... Disable Asynchronous Awake (for NT, LT-S and Int. NT mode)
Setting this bit to “1” disables the Asynchronous Awake function of the transceiver.
CI_CS ... C/I Channel Selection
The channel selection for D-channel and C/I-channel is done in the channel select bits
CH2-0 of register TR_CR (for the transceiver) and DCI_CR (for the C/I-channel
controller).
0: A write access to CS2-0 has effect on the configuration of D- and C/I-channel,
whereas a read access delivers the D-channel configuration only.
1: A write access to CS2-0 has effect on the configuration of the C/I-channel only,
whereas a read access delivers the C/I-channel configuration only.
TIC_DIS ... TIC Bus Disable
0: The last octet of IOM channel 2 (12th timeslot) is used as TIC bus (in a frame timing
mode with 12 timeslots only).
1: The TIC bus is disabled. The last octet of the last IOM time slot (TS 11) can be used
as every time slot.
Data Sheet
7
IOM_CR - Control Register IOM Data
SPU
DIS_
H
AW
CI_CS TIC_
DIS
Chapter
158
EN_
BCL
3.7.6.
CLKM DIS_
Detailed Register Description
OD
0
DIS_
IOM
RD/WR (57)
PEB 3081
PEF 3081
2000-09-27