SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet
SAA7109EEB
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SAA7109EEB Summary of contents
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DATA SHEET SAA7108E; SAA7109E PC-CODEC Product specification Supersedes data of 2001 Dec 12 INTEGRATED CIRCUITS 2004 Mar 16 ...
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Philips Semiconductors PC-CODEC CONTENTS 1 FEATURES 1.1 Video decoder 1.2 Video scaler 1.3 Video encoder 1.4 Common features 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION 6 BLOCK DIAGRAMS 7 PINNING 8 FUNCTIONAL DESCRIPTION OF DIGITAL ...
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Philips Semiconductors PC-CODEC 1 FEATURES 1.1 Video decoder Six analog inputs, internal analog source selectors, e.g. 6 CVBS or (2 Y/C and 2 4 CVBS) Two analog preprocessing channels in differential CMOS style for best S/N-performance Fully programmable static gain ...
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Philips Semiconductors PC-CODEC Selectable cross-colour reduction to improve CVBS output Non-interlaced C -Y-C or RGB input at maximum sampling Downscaling from and up to 20% upscaling ...
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Philips Semiconductors PC-CODEC 3 GENERAL DESCRIPTION The SAA7108E; SAA7109E is a new multi-standard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 specifications. It enables hardware manufacturers to implement versatile video ...
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Philips Semiconductors PC-CODEC 6 BLOCK DIAGRAMS handbook, full pagewidth CVBS, Y/C analog video input Y /RGB digital video graphics input 2004 Mar 16 digital video input and output X port ANALOG VIDEO ACQUISITION AND DEMODULATOR VIDEO DECODER ...
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Acrobat reader. white to force landscape pages to be ... V DDEe V V DDAe DDXe A10, B6 C1, C2, B1, B9, ...
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Acrobat reader. white to force landscape pages to be ... XPD [ 7:0 ] LLC2 RTS0 XCLK LLC RTCO RTS1 XDQ (1) M14 L14 ...
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Philips Semiconductors PC-CODEC 7 PINNING SYMBOL PIN TYPE PD7 A2 PD4 A3 TRSTe A4 XTALIe A5 XTALOe A6 DUMP SSXe RSET A9 V A10 DDAe HPD0 A11 HPD3 A12 HPD7 A13 PD9 B1 PD8 B2 PD5 B3 ...
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Philips Semiconductors PC-CODEC SYMBOL PIN TYPE GREEN_VBS_CVBS C7 RED_CR_C DDAe TEST2 C10 HPD2 C11 HPD5 C12 IPD1 C13 IPD5 C14 TDOe D1 RESET D2 TMSe DDIe V D5 SSIe V D6 DDXe VSM D7 ...
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Philips Semiconductors PC-CODEC SYMBOL PIN TYPE FSVGC G1 SDAe G2 CBO G3 PIXCLKO G4 V G11 DDEd IGPH G12 IGP1 G13 ITRI G14 PD2 H1 PD1 H2 PD0 SSEd V H11 SSEd ICLK H12 TEST0 H13 IDQ ...
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Philips Semiconductors PC-CODEC SYMBOL PIN TYPE V L6 SSEd V L7 DDEd V L8 DDXd V L9 DDEd RTS1 L10 V L11 DDId SDAd L12 RTCO L13 LLC2 L14 XPD2 M1 XPD1 M2 XCLK M3 XDQ M4 TMSd M5 TCKd ...
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Philips Semiconductors PC-CODEC SYMBOL PIN TYPE XTALId P2 XTALOd P3 XTOUTd SSXd AI24 P6 AI23 P7 AI2D P8 AI22 P9 AI21 P10 AI12 P11 AI1D P12 AI11 P13 Notes 1. Pin type input ...
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Acrobat reader. white to force landscape pages to be ... Table 1 Pin assignment (top view PD7 PD4 ...
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Philips Semiconductors PC-CODEC 8 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO ENCODER PART The digital video encoder encodes digital luminance and colour difference signals (C -Y-C B into analog CVBS, S-video and, optionally, RGB or C -Y-C signals. NTSC M, PAL B/G ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth (dB ( (1) SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth (dB (1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 1; ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth (dB Fig.9 Luminance transfer characteristic in RGB (excluding scaler). handbook, full pagewidth (dB ...
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Philips Semiconductors PC-CODEC 8.1 Reset conditions To activate the reset a pulse at least of 2 crystal clocks duration is required. During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC, CBO, HSVGC and TTX_SRES are ...
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Philips Semiconductors PC-CODEC It can have any position in the bit map. The actual position registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. While it is not possible to move the hot spot ...
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Philips Semiconductors PC-CODEC 8.8 FIFO The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underflow or overflow condition can ...
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Philips Semiconductors PC-CODEC Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion ...
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Philips Semiconductors PC-CODEC Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. Only vertical frequencies of 50 and 60 Hz are allowed with the SAA7108E; SAA7109E. In slave mode, it ...
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Philips Semiconductors PC-CODEC For vertical, the procedure is the same Hz, the first line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table 112. 240 ...
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Philips Semiconductors PC-CODEC 8.18 Input levels and formats The SAA7108E; SAA7109E accepts digital Y, C “ITU-R BT.601” ; see Table 24. For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated for by independent gain ...
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Philips Semiconductors PC-CODEC Table 7 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 8 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 9 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 10 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 11 Y scaler programming at NTSC, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 12 Y scaler programming at NTSC, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 13 Y scaler programming at NTSC, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 14 Y scaler programming at NTSC, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 212 4 29 212 2 31 212 0 33 212 2 35 ...
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Philips Semiconductors PC-CODEC Table 15 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 16 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 17 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 18 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 19 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 20 Y scaler programming at PAL, input frame size: 640 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 21 Y scaler programming at PAL, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 22 Y scaler programming at PAL, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 23 Y scaler programming at PAL, input frame size: 800 TV LINE OFFSET FAL Regular size (horizontal TV size: 640 pixels, offset 10 pixels) 255 4 35 255 2 37 255 0 39 255 2 41 ...
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Philips Semiconductors PC-CODEC Table 24 “ITU-R BT.601” signal component levels SIGNALS COLOUR White 235 128 128 Yellow 210 16 146 Cyan 170 166 16 Green 145 54 34 Magenta 106 202 222 Red 81 90 240 ...
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Philips Semiconductors PC-CODEC Table 29 Pin assignment for input format 8-BIT INTERLACED C (ITU-R BT.656, 27 MHz CLOCK) RISING RISING CLOCK CLOCK PIN EDGE EDGE PD7 ...
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Philips Semiconductors PC-CODEC 9 FUNCTIONAL DESCRIPTION OF DIGITAL VIDEO DECODER PART 9.1 Decoder 9.1.1 A NALOG INPUT PROCESSING The SAA7108E; SAA7109E offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and ...
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Philips Semiconductors PC-CODEC 9.1.2.1 Clamping The clamping control circuit controls the correct clamping of the analog input signals. A coupling capacitor is used to store and filter the clamping voltage. An internal digital clamp comparator generates the information with respect ...
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Acrobat reader. white to force landscape pages to be ... P6 AI24 P7 AI23 SOURCE P8 AI2D SWITCH CLAMP P9 AI22 CIRCUIT P10 AI21 ...
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Philips Semiconductors PC-CODEC NO ACTION STOP X = system variable (IAGV FGVI) > GUDL. VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value. 2004 Mar 16 ANALOG ...
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Philips Semiconductors PC-CODEC NO BLANKING ACTIVE 1 CLL CLAMP WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. 2004 ...
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Acrobat reader. white to force landscape pages to be ... CVBS-IN DELAY or Y-IN LDEL COMPENSATION YCOMB QUADRATURE MODULATOR CVBS-IN QUADRATURE LOW-PASS 1 or ...
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Philips Semiconductors PC-CODEC 9.1.3.1 Chrominance path The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 ...
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Philips Semiconductors PC-CODEC (dB (1) LCBW[2:0] = 000. 51 (2) LCBW[2:0] = 010. 54 (3) LCBW[2:0] = 100. 57 (4) LCBW[2:0] ...
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Philips Semiconductors PC-CODEC (dB (1) LCBW[2:0] = 000. 51 (2) LCBW[2:0] = 010. 54 (3) LCBW[2:0] = 100. 57 (4) LCBW[2:0] ...
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Philips Semiconductors PC-CODEC 9.1.3.2 Luminance path The rejection of the chrominance components within the 9-bit CVBS or Y input signal is done by subtracting the re-modulated chrominance signal from the CVBS input. The comb filtered C -C components are interpolated ...
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Philips Semiconductors PC-CODEC (dB (1) LCBW[2:0] = 000. 51 (2) LCBW[2:0] = 010. 54 (3) LCBW[2:0] = 100. 57 (4) LCBW[2:0] ...
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Philips Semiconductors PC-CODEC (dB (1) LCBW[2:0] = 000 51 (2) LCBW[2:0] = 010 54 (3) LCBW[2:0] = 100 57 (4) LCBW[2:0] ...
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Philips Semiconductors PC-CODEC (dB (1) LCBW[2:0] = 000. 51 (2) LCBW[2:0] = 010. 54 (3) LCBW[2:0] = 100. 57 (4) LCBW[2:0] ...
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Philips Semiconductors PC-CODEC (dB (1) LCBW[2:0] = 000. 51 (2) LCBW[2:0] = 010. 54 (3) LCBW[2:0] = 100. 57 (4) LCBW[2:0] ...
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Philips Semiconductors PC-CODEC 9 V (dB (1) LUFI[3:0] = 0001. (2) LUFI[3:0] = 0010. 2 (3) LUFI[3:0] = 0011. (4) LUFI[3:0] = 0100. 1 (5) LUFI[3:0] = 0101. (6) LUFI[3:0] = 0110. 0 (7) ...
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Philips Semiconductors PC-CODEC 9.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels The resulting Y (CVBS) and Chrominance saturation control by DSAT7 to DSAT0 Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to ...
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Philips Semiconductors PC-CODEC 255 209 LUMINANCE 71 60 SYNC 1 a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). CVBS levels with default settings RAWG[7: and RAWO[7:0] = 128. Equation for modification of the raw data ...
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Philips Semiconductors PC-CODEC 9.1.4 S YNCHRONIZATION The prefiltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz by a low-pass filter. The sync pulses are sliced and fed to the phase detectors where ...
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Philips Semiconductors PC-CODEC CE CE XTALO LLCINT RESINT LLC RES (internal reset) some ms POC = Power-on Control chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked ...
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Philips Semiconductors PC-CODEC 9.2 Decoder output formatter The output interface block of the decoder part contains the ITU 656 formatter for the expansion port data output XPD7 to XPD0 (see Section 10.4.1) and the control circuit for the signals needed ...
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Acrobat reader. white to force landscape pages to be ... Table 34 Relationship of LCR to line numbers in 525 lines/60 Hz systems (part ...
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Philips Semiconductors PC-CODEC 623 ITU counting 622 309 310 single field counting CVBS HREF F_ITU656 (1) V123 VSTO [ 8 134H VGATE FID ITU counting 309 310 single field counting 309 310 CVBS HREF F_ITU656 (1) V123 VSTO ...
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Philips Semiconductors PC-CODEC ITU counting 525 single field counting 262 CVBS HREF F_ITU656 (1) V123 VSTO [ 8 101H VGATE FID ITU counting 263 262 single field counting 262 263 CVBS HREF F_ITU656 (1) V123 VSTO [ 8:0 ...
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Philips Semiconductors PC-CODEC CVBS input expansion port data output HREF (50 Hz) HS (50 Hz) programming range (step size: 8/LLC) HREF (60 Hz) HS (60 Hz) programming range (step size: 8/LLC) The signals HREF, HS, CREF2 and CREF are available ...
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Philips Semiconductors PC-CODEC 9.3 Scaler The High Performance video Scaler (HPS) is based on the system as implemented in the SAA7140, but enhanced in some aspects. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow ...
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Philips Semiconductors PC-CODEC In VBI pass through operation the processing of prescaler and vertical scaling has to be disabled, however the horizontal fine scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding factor 3.5 can ...
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Philips Semiconductors PC-CODEC Table 38 Processing trigger and start XDV1 XDV0 XDH 92H[5] 92H[4] 92H[ 9.3.1.2 Task handling The task handler controls the switching between the two programming register sets. It ...
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Philips Semiconductors PC-CODEC 9.3.1.3 Output field processing As a reference for the output field processing, two signals are available for the back-end hardware. These signals are the input field ID from the scaler source and a TOGGLE flag, which shows ...
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Acrobat reader. white to force landscape pages to be ... Table 39 Example for field processing (1) SUBJECT EXAMPLE 1 1/1 1/2 2/1 1/1 ...
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Philips Semiconductors PC-CODEC 9.3.2 H ORIZONTAL SCALING The overall horizontal scaling factor has to be split into a binary and a rational value according to the following output pixel equation: H scale ratio = ----------------------------- - input pixel 1 H ...
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Philips Semiconductors PC-CODEC Remark: Due to bandwidth considerations XPSC[5:0] and XACL[5:0] can be chosen differently to the previously mentioned equations or Table 41, as the horizontal phase scaling is able to scale in the range from zooming up by factor ...
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Philips Semiconductors PC-CODEC (dB (1) PFY[1:0] = 01. 42 (2) PFY[1:0] = 10. 0 (3) PFY[1: (dB) 0 ...
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Philips Semiconductors PC-CODEC (dB XC2_1 = 0; Zero’ ------------------------ - XACL with XACL = ...
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Philips Semiconductors PC-CODEC Table 41 Example of XACL[5:0] usage PRESCALE XPSC FOR LOWER BANDWIDTH RATIO [5:0] XACL[5: ...
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Philips Semiconductors PC-CODEC 9.3.2.2 Horizontal fine scaling (variable phase delay filter; subaddresses A8H to AFH and D8H to DFH) The horizontal fine scaling (VPD) should operate at scaling 1 ratios between and 2 (0.8 and 1.6), but can also be ...
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Philips Semiconductors PC-CODEC LPI mode: In the linear phase interpolation mode (YMODE = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line ...
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Philips Semiconductors PC-CODEC Depending on the input signal (interlaced or non-interlaced) and the task processing ( field reduced processing with one or two tasks, see examples in Section 9.3.1.3), other combinations may also be possible, but the basic ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth field 1 upper B A 1024 Offset = ------------ - = line shift input line shift ...
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Philips Semiconductors PC-CODEC Table 43 Vertical phase offset usage; assignment of the phase offsets DETECTED INPUT TASK STATUS BIT FIELD upper lines upper lines lower lines lower lines ...
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Philips Semiconductors PC-CODEC Table 44 Data types supported by the data slicer block DATA TYPE STANDARD TYPE NUMBER 0000 teletext EuroWST, CCST 0001 European Closed Caption 0010 VPS 0011 wide screen signalling bits 0100 US teletext (WST) 0101 US Closed ...
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Philips Semiconductors PC-CODEC 9.5.1 S CALER OUTPUT FORMATTER ( 93H SUBADDRESSES AND The output formatter organizes the packing into the output FIFO. The following formats are available ...
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Philips Semiconductors PC-CODEC 9.5.2 V FIFO ( IDEO SUBADDRESS The video FIFO at the scaler output contains 32 Dwords. That corresponds to 64 pixels in 16-bit Y-C format. But as the entire scaler can act as a pipeline buffer, the ...
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Philips Semiconductors PC-CODEC 9.5.5 D ATA STREAM CODING AND REFERENCE SIGNAL ( GENERATION SUBADDRESSES As horizontal and vertical reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. Alternatively, the horizontal ...
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Acrobat reader. white to force landscape pages to be ... invalid data or end of raw VBI line timing reference code internal header ... ...
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Philips Semiconductors PC-CODEC Table 50 Bytes stream of the data slicer NICK COMMENT NAME DID, subaddress SAV, 5DH = 00H EAV subaddress 5DH; bit subaddress 5DH bit 5 = 3EH; note 5 subaddress 5DH bit 5 = ...
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Philips Semiconductors PC-CODEC 9.6 Audio clock generation (subaddresses 30H to 3FH) The SAA7108E; SAA7109E incorporates the generation of a field-locked audio clock auxiliary function for video capture. An audio sample clock, that is locked to the field frequency, ...
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Philips Semiconductors PC-CODEC 9.6.2 S ASCLK ALRCLK IGNALS AND Two binary divided signals ASCLK and ALRCLK are provided for slower serial digital audio signal transmission and for channel-select. The frequencies of these signals are defined by the parameters: SDIV[5:0] 38H[5:0] ...
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Philips Semiconductors PC-CODEC 10 INPUT/OUTPUT INTERFACES AND PORTS OF DIGITAL VIDEO DECODER PART The SAA7108E; SAA7109E has 5 different I/O interfaces. These are: Analog video input interface, for analog CVBS and/or Y and C input signals Audio clock port Digital ...
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Philips Semiconductors PC-CODEC 10.3 Clock and real-time synchronization signals A crystal accurate frequency reference is required for the generation of the line-locked video (pixel) clock LLC, and the frame-locked audio serial bit clock. An oscillator is built-in, for fundamental or ...
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Philips Semiconductors PC-CODEC 10.4 Video expansion port (X port) The expansion port is intended for transporting video streams of image data from other digital video circuits such as MPEG encoder/decoder and video phone codec, to the image port (I port); ...
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Philips Semiconductors PC-CODEC 10.4.1 X PORT CONFIGURED AS OUTPUT If the data output is enabled at the expansion port, then the data stream from the decoder is present. The data format of the 8-bit data bus is dependent on the ...
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Philips Semiconductors PC-CODEC Table 59 SAV/EAV format on expansion port XPD7 to XPD0 BIT 6 BIT 7 (F) 1 field bit 1st field 2nd field for vertical timing see Tables 60 and 61 Table ...
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Philips Semiconductors PC-CODEC 10.4.2 X PORT CONFIGURED AS INPUT If data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by ...
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Philips Semiconductors PC-CODEC The following deviations from “ITU 656 recommendation” are implemented at the SAA7108E; SAA7109E image port interface: SAV and EAV codes are only present in those lines, where data transferred, i.e. active video lines, or ...
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Philips Semiconductors PC-CODEC 10.6 Host port for 16-bit extension of video data I/O (H port) The H port, pins HPD, can be used to extend the data I/O paths to 16-bit. The I port has functional priority. If I8_16[93H[6]] is ...
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Philips Semiconductors PC-CODEC ICLK IDQ IPD [ 7:0 ] IGPH Fig.40 Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0). ICLK IDQ IPD [ 7 ...
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Philips Semiconductors PC-CODEC ICLK IDQ IPD [ 7 IGPH Fig.42 Output timing at the I port for serial 8-bit data at end of a line (ICODE = 0). ICLK IDQ IPD [ 7 ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth IDQ IGPH IGPV handbook, full pagewidth ICLK IDQ IPD [ 7 HPD [ 7 sliced data flag on IGP0 or IGP1 Fig.45 Output timing for sliced ...
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Philips Semiconductors PC-CODEC 11 BOUNDARY SCAN TEST The SAA7108E; SAA7109E has built-in logic and 2 times 5 dedicated pins to support boundary scan testing, separately for the encoder and decoder part, which allows board testing without special hardware (nails). The ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth TDIe SAA7108E (or TDId) TDIe SAA7109E (or TDId) 12 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and grounded (0 V); all supply pins connected ...
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Philips Semiconductors PC-CODEC 13 THERMAL CHARACTERISTICS SYMBOL PARAMETER R thermal resistance from junction to ambient th(j-a) Note 1. The overall R value can vary depending on the board layout. To minimize the effective R th(j-a) ground pins must be connected ...
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Philips Semiconductors PC-CODEC SYMBOL PARAMETER duty factor t /T HIGH duty factor t /T HIGH t rise time r t fall time f Input timing t input data set-up time SU;DAT t input data hold time HD;DAT Crystal oscillator f ...
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Philips Semiconductors PC-CODEC Notes 2 1. Minimum value for I C-bus bit DOWNA = Minimum value for I C-bus bit DOWND = 1. 3. The data is for both input and output direction. 4. This parameter is ...
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Philips Semiconductors PC-CODEC SYMBOL PARAMETER 9-bit analog-to-digital converters B analog bandwidth differential phase diff (amplifier plus anti-alias filter bypassed) G differential gain (amplifier diff plus anti-alias filter bypassed) f ADC clock frequency clk(ADC) DLE DC differential linearity dc(d) error ILE ...
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Philips Semiconductors PC-CODEC SYMBOL PARAMETER duty factors for t LLCH and t /t LLC2H LLC2 t rise time LLC and LLC2 r t fall time LLC and LLC2 f t delay time between LLC d(LLC-LLC2) and LLC2 output Horizontal PLL ...
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Philips Semiconductors PC-CODEC SYMBOL PARAMETER C parallel capacitance 0 Clock input timing (XCLK) T cycle time cy duty factors for t LLCH t rise time r t fall time f Data and control signal input timing X port, related to ...
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Philips Semiconductors PC-CODEC SYMBOL PARAMETER t output delay time o(d) ICLK input timing T cycle time cy Notes 1. The levels must be measured with load circuits; 1 (TTL load The effects of rise ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth HSVGC CBO PD handbook, full pagewidth HSVGC VSVGC CBO 2004 Mar 16 XOFS IDEL XPIX HLEN Fig.48 Horizontal input timing. YOFS YPIX Fig.49 Vertical input timing. 112 Product specification SAA7108E; SAA7109E MHB905 MHB906 ...
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Philips Semiconductors PC-CODEC 16.1.1 T ELETEXT TIMING Time t is the time needed to interpolate input data TTX FD and insert it into the CVBS and VBS output signal, such that it appears 9.78 s (PAL) or ...
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Philips Semiconductors PC-CODEC 16.2 Digital video decoder part handbook, full pagewidth clock input XCLK t SU;DAT data and control inputs (X port) input XDQ data and control outputs X port, I port clock outputs LLC, LLC2, XCLK, ICLK and ICLK ...
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Philips Semiconductors PC-CODEC 17 APPLICATION INFORMATION handbook, full pagewidth 32.11 MHz V DDP R12 AUDIO2 4 C-BUS_Adr:40H/42H V DDP R13 RCON0 4.7 k R19 AI24 18 R17 AI23 18 R16 AI22 18 R18 AI21 18 R15 AI12 ...
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Acrobat reader. white to force landscape pages to be ... V DD (EF4 (ID4 (XD6) R33 0 SDA SCL G2 ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth SAA7108E SAA7109E P2 P3 XTALId XTALOd 32.11 MHz 4 (1a) With 3rd-harmonic quartz. Crystal load = 8 pF. handbook, full pagewidth SAA7108E SAA7109E P2 P3 XTALId XTALOd ...
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Philips Semiconductors PC-CODEC handbook, full pagewidth A5 XTALIe 4 (1a) With 3rd-harmonic quartz. Crystal load = 8 pF. handbook, full pagewidth A5 XTALIe 27.00 MHz (2a) With direct clock. 2004 Mar 16 SAA7108E SAA7109E A6 XTALOe 27.00 ...
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Philips Semiconductors PC-CODEC 17.1 Analog output voltages The analog output voltages are dependent on the total load (typical value 37.5 ), the digital gain parameters and 2 the I C-bus settings of the DAC reference currents (analog settings). The digital ...
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Acrobat reader. white to force landscape pages to be ... C-BUS DESCRIPTION 18.1 Digital video encoder part Table 66 Slave receiver ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Gain U 5B GAINU7 Gain V 5C GAINV7 Gain ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) TTX even request vertical end 79 TTXEVE7 First active ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Border colour Y A2 BCY7 Border colour U A3 ...
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Philips Semiconductors PC-CODEC 2 18.1 BUS FORMAT 2 Table 67 I C-bus write access to control registers; see Table SUBADDRESS 2 Table 68 I C-bus write access ...
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Philips Semiconductors PC-CODEC 18.1.2 S LAVE RECEIVER Table 73 Subaddress 16H DATA BYTE DACF output level adjustment fi steps for all DACs; default after reset is 00H; see Table 74 Table 74 Fine adjustment of DAC output voltage ...
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Philips Semiconductors PC-CODEC Table 77 Subaddress 1BH LOGIC DATA BYTE LEVEL MSM 0 monitor sense mode off; RCOMP, GCOMP and BCOMP bits are not valid; default after reset 1 monitor sense mode on RCOMP 0 check comparator at DAC on ...
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Philips Semiconductors PC-CODEC Table 81 Subaddresses 2AH to 2CH LOGIC DATA BYTE LEVEL CG LSB of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the ...
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Philips Semiconductors PC-CODEC Table 84 Subaddress 3AH LOGIC DATA BYTE LEVEL CBENB 0 data from input ports is encoded 1 colour bar with fixed colours is encoded SYMP 0 horizontal and vertical trigger is taken from FSVGC or both VSVGC ...
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Philips Semiconductors PC-CODEC Table 87 Subaddress 5AH; note 1 DATA BYTE DESCRIPTION CHPS phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees Note 1. The default after reset is 00H. ...
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Philips Semiconductors PC-CODEC Table 91 Subaddress 5EH DATA BYTE DESCRIPTION BLNNL variable blanking level Notes 1. Output black level/IRE = BLNNL 2. Output black level/IRE = BLNNL Table 92 Subaddress 5FH DATA BYTE CCRS select cross-colour reduction filter in luminance; ...
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Philips Semiconductors PC-CODEC Table 95 Subaddress 62H DATA BYTE DESCRIPTION BSTA amplitude of colour burst; input representation in accordance with “ITU-R BT.601” Table 96 Subaddresses 63H to 66H (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION FSC0 to f ...
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Philips Semiconductors PC-CODEC Table 99 Subaddress 6DH DATA BYTE VTRIG sets the vertical trigger phase related to chip-internal vertical input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines; variation range of VTRIG = 0 ...
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Philips Semiconductors PC-CODEC Table 104 Subaddress 6FH DATA LOGIC BYTE LEVEL CCEN enables individual line 21 encoding; see Table 105 TTXEN 0 disables teletext insertion; default after reset 1 enables teletext insertion SCCLN selects the actual line, where Closed Caption ...
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Philips Semiconductors PC-CODEC Table 110 Subaddresses 76H, 77H and 7CH DATA BYTE TTXOVS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2 (CLK2EN = 0) in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + ...
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Philips Semiconductors PC-CODEC Table 115 Subaddresses 81H to 83H DATA BYTE PCL defines the frequency of the synthesized pixel clock PIXCLKO; PCL f = ---------- - PIXCLK 24 2 640 480 to PAL B/G: PCL = 1B5A73H (as by strapping ...
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Philips Semiconductors PC-CODEC LOGIC DATA BYTE LEVEL ILC 0 if hardware cursor insertion is active, set LOW for non-interlaced input signals 1 if hardware cursor insertion is active, set HIGH for interlaced input signals YFIL 0 luminance sharpness booster disabled ...
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Philips Semiconductors PC-CODEC Table 124 Subaddress 99H DATA BYTE IDEL input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel Table 125 Subaddresses 9AH and 9CH DATA BYTE XINC incremental fraction ...
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Philips Semiconductors PC-CODEC Table 132 Subaddresses F0H to F2H DATA BYTE CC1R, CC1G RED, GREEN and BLUE portion of first cursor colour and CC1B Table 133 Subaddresses F3H to F5H DATA BYTE CC2R, CC2G RED, GREEN and BLUE portion of ...
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Philips Semiconductors PC-CODEC Table 139 Subaddress FDH LOGIC DATA BYTE LEVEL LUTOFF 0 colour look-up table is active 1 colour look-up table is bypassed CMODE 0 cursor mode; input colour will be inverted 1 auxiliary cursor colour will be inserted ...
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Philips Semiconductors PC-CODEC 18.1.3 S LAVE TRANSMITTER Table 142 Slave transmitter (slave address 89H) REGISTER SUBADDRESS FUNCTION Status byte 00H Chip ID 1CH FIFO status 80H Table 143 Subaddress 00H LOGIC DATA BYTE LEVEL VER version identification of the device: ...
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Philips Semiconductors PC-CODEC 18.2 Digital video decoder part 2 18.2 BUS FORMAT S SLAVE ADDRESS W S SLAVE ADDRESS W Sr SLAVE ADDRESS R 2 Table 146 Description of I C-bus format; note 1 CODE S START condition ...
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Philips Semiconductors PC-CODEC Table 147 Subaddress description and access SUBADDRESS 00H chip version F0H to FFH reserved Video decoder: 01H to 2FH 01H to 05H front-end part 06H to 19H decoder part 1AH to 1EH reserved 1FH video decoder status ...
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Acrobat reader. white to force landscape pages to be ... 2 Table 148 I C-bus receiver/transmitter overview SUB REGISTER FUNCTION ADDR. D7 (HEX) Chip ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX) Miscellaneous, 17 LLCE VGATE configuration and MSBs Raw ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX) Horizontal offset for slicer 59 HOFF7 Vertical offset ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX 90H BFH ASK DEFINITION REGISTERS ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX) Horizontal phase scaling Horizontal luminance scaling A8 XSCY7 ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX) Vertical luminance phase BF YPY37 offset ‘11’ T ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX) Horizontal phase scaling Horizontal luminance scaling D8 XSCY7 ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. D7 (HEX) Vertical luminance phase EC YPY07 offset ‘00’ Vertical ...
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Philips Semiconductors PC-CODEC 18.2.2.3 Subaddress 02H Table 151 Analog input control 1 (AICO1); 02H[7:0] BIT DESCRIPTION 7 and 6 analog function select; see Fig.14 5 and 4 update hysteresis for 9-bit gain; see Fig. mode selection Note ...
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Philips Semiconductors PC-CODEC AI24 AI23 AD2 AI22 AI21 AI12 AD1 AI11 Fig.57 Mode 0; CVBS (automatic gain). AI24 AI23 AD2 AI22 AI21 AI12 AD1 AI11 Fig.59 Mode 2; CVBS (automatic gain). AI24 AI23 AD2 AI22 AI21 AI12 AD1 AI11 Fig.61 ...
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Philips Semiconductors PC-CODEC AI24 AI23 AD2 AI22 AI21 AI12 AD1 AI11 2 I C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1 (full luminance bandwidth). Fig.63 Mode (gain channel 2 adjusted via ...
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Philips Semiconductors PC-CODEC 18.2.2.4 Subaddress 03H Table 152 Analog input control 2 (AICO2); 03H[6:0] BIT DESCRIPTION 6 HL not reference select 5 AGC hold during vertical blanking period 4 white peak control off 3 automatic gain control integration 2 gain ...
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Philips Semiconductors PC-CODEC 18.2.2.7 Subaddress 06H Table 155 Horizontal sync start; 06H[7:0] DELAY TIME (STEP SIZE = 8/LLC) 128... 109 (50 Hz) 128... 108 (60 Hz) 108 (50 Hz)... 107 (60 Hz)... ...108 (50 Hz) ...107 (60 Hz) 109...127 (50 ...
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Philips Semiconductors PC-CODEC 18.2.2.9 Subaddress 08H Table 157 Sync control; 08H[7:0] BIT DESCRIPTION 7 automatic field detection 6 field selection 5 forced ODD/EVEN toggle 4 and 3 horizontal time constant selection 2 horizontal PLL 1 and 0 vertical noise reduction ...
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Philips Semiconductors PC-CODEC 18.2.2.10 Subaddress 09H Table 158 Luminance control; 09H[7:0] BIT DESCRIPTION 7 chrominance trap/comb filter bypass 6 adaptive luminance comb filter 5 processing delay in non comb filter mode 4 remodulation bandwidth for luminance; see Figs 20 to ...
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Philips Semiconductors PC-CODEC 18.2.2.12 Subaddress 0BH Table 160 Luminance contrast control: decoder part; 0BH[7:0] GAIN DCON7 1.984 (maximum) 1.063 (ITU level) 1.0 0 (luminance off) 1 (inverse luminance) 2 (inverse luminance) 18.2.2.13 Subaddress 0CH Table 161 Chrominance saturation control: decoder ...
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Philips Semiconductors PC-CODEC 18.2.2.15 Subaddress 0EH Table 163 Chrominance control 1; 0EH[7:0] BIT DESCRIPTION 7 clear DTO colour standard selection 3 disable chrominance vertical filter and PAL phase error correction 2 fast colour time constant 0 adaptive ...
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Philips Semiconductors PC-CODEC 18.2.2.17 Subaddress 10H Table 165 Chrominance control 2; 10H[7:0] BIT DESCRIPTION 7 and 6 fine offset adjustment B 5 and 4 fine offset adjustment R 3 chrominance bandwidth; see Figs 18 and combined ...
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Philips Semiconductors PC-CODEC 18.2.2.19 Subaddress 12H Table 167 RT signal control: RTS0 output; 12H[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]]. RTS0 OUTPUT 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.31) CREF2 (6.75 ...
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Philips Semiconductors PC-CODEC Table 168 RT signal control: RTS1 output; 12H[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]]. RTS1 OUTPUT CONTROL 3-state Constant LOW CREF (13.5 MHz toggling pulse; see Fig.31) CREF2 (6.75 MHz toggling ...
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Philips Semiconductors PC-CODEC 18.2.2.20 Subaddress 13H Table 169 RT/X port output control; 13H[7:0] BIT DESCRIPTION 7 RTCO output enable 6 X port XRH output selection 5 and 4 X port XRV output selection 3 horizontal lock indicator selection 2 to ...
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Philips Semiconductors PC-CODEC 18.2.2.21 Subaddress 14H Table 170 Analog/ADC/compatibility control; 14H[7:0] BIT DESCRIPTION 7 compatibility bit for SAA7199 6 update time interval for AGC value 5 and 4 analog test select 3 XTOUTd output enable 2 decoder status byte selection; ...
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Acrobat reader. white to force landscape pages to be ... 18.2.2.22 Subaddress 15H Table 171 VGATE start; FID polarity change; 17H[0] and 15H[7:0] Start ...
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Acrobat reader. white to force landscape pages to be ... 18.2.2.23 Subaddress 16H Table 172 VGATE stop; 17H[1] and 16H[7:0] Stop of VGATE pulse ...
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Philips Semiconductors PC-CODEC 18.2.2.24 Subaddress 17H Table 173 Miscellaneous/VGATE MSBs; 17H[7:6] and 17H[2:0] BIT DESCRIPTION 7 LLC output enable 6 LLC2 output enable 2 alternative VGATE position 1 MSB VGATE stop 0 MSB VGATE start 18.2.2.25 Subaddress 18H Table 174 ...
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Philips Semiconductors PC-CODEC 18.2.2.27 Subaddress 1FH Table 176 Status byte video decoder; 1FH[7:0]; read only register BIT DESCRIPTION 7 status bit for interlace detection 6 status bit for horizontal and vertical loop status bit for locked horizontal frequency 5 identification ...
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Philips Semiconductors PC-CODEC 18.2.3.2 Subaddresses 34H to 36H Table 178 Audio master clock (AMCLK) nominal increment SUBADDRESS 34H ACNI7 35H ACNI15 36H 18.2.3.3 Subaddress 38H Table 179 Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK) SUBADDRESS 38H ...
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Philips Semiconductors PC-CODEC 18.2.4.2 Subaddresses 41H to 57H Table 183 Line control register; LCR2 to LCR24 (41H to 57H); see Sections 9.2 and 9.4 NAME DESCRIPTION WST625 teletext EuroWST, CCST CC625 European Closed Caption VPS video programming service WSS wide ...
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Philips Semiconductors PC-CODEC 18.2.4.5 Subaddress 5AH Table 186 Vertical offset for slicer; slicer set 5AH and 5BH VERTICAL OFFSET Minimum value 0 Maximum value 312 Value for 50 Hz 625 lines input Value for 60 Hz 525 lines input 18.2.4.6 ...
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Philips Semiconductors PC-CODEC 18.2.4.9 Subaddress 60H Table 190 Slicer status byte 0; 60H[6:2]; read only register BIT DESCRIPTION 6 framing code valid 5 framing code valid 4 VPS valid 3 PALplus valid 2 Closed Caption valid 18.2.4.10 Subaddresses 61H and ...
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Philips Semiconductors PC-CODEC Table 193 Global control 1; global set 80H[3:0]; note 1 I PORT AND SCALER BACK-END CLOCK SELECTION ICLK output and back-end clock is line-locked clock LLC from decoder ICLK output and back-end clock is XCLK from X ...
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Philips Semiconductors PC-CODEC Table 196 I port signal definitions; global set 84H[7:6] and 86H[5] I PORT SIGNAL DEFINITIONS IGP0 is output field ID, as defined by OFIDC[90H[6]] IGP0 is A/B task flag, as defined by CONLH[90H[7]] IGP0 is sliced data ...
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Philips Semiconductors PC-CODEC Table 199 X port signal definitions text slicer; global set 85H[7:5]; note 1 X PORT SIGNAL DEFINITIONS TEXT SLICER Video data limited to range 1 to 254 Video data limited to range 8 to 247 Dword byte ...
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Philips Semiconductors PC-CODEC Table 201 I port FIFO flag control and arbitration; global set 86H[7:4]; note 1 FUNCTION See subaddress 84H: IDG11 and IDG10 See subaddress 84H: IDG01 and IDG00 I port signal definitions I port data output inhibited Only ...
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Philips Semiconductors PC-CODEC Table 203 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1 OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL ICLK default output phase 1 ICLK phase shifted by clock cycle 2 ...
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Philips Semiconductors PC-CODEC 18.2.5.3 Subaddress 88H Table 205 Power save control; global set 88H[7:4]; note 1 POWER SAVE CONTROL DPROG = 0 after reset DPROG = 1 can be used to assign that the device has been programmed; this bit ...
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Philips Semiconductors PC-CODEC 18.2.5.4 Subaddress 8FH Table 207 Status information scaler part; 8FH[7:0]; read only register 2 I C-BUS BIT STATUS BIT 7 XTRI status on input pin XTRI, if not used for 3-state control, usable as hardware flag for ...
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Philips Semiconductors PC-CODEC Table 210 Task handling control; register set A [90H[2:0]] and B [C0H[2:0]]; note 1 EVENT HANDLER CONTROL Event handler triggers immediately after finishing a task Event handler triggers with next V-sync Event handler triggers with field ID ...
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Philips Semiconductors PC-CODEC Table 212 X port formats and configuration; register set A [91H[2:0]] and B [C1H[2:0]]; note 1 SCALER INPUT FORMAT AND CONFIGURATION FORMAT CONTROL Input is Y like sampling scheme B R ...
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Philips Semiconductors PC-CODEC Table 214 X port input reference signal definitions; register set A [92H[3:0]] and B [C2H[3:0]]; note 1 X PORT INPUT REFERENCE SIGNAL DEFINITIONS XCLK input clock and XDQ input qualifier are needed Data rate is defined by ...
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Philips Semiconductors PC-CODEC Table 216 I port output format and configuration; register set A [93H[4:0]] and B [C3H[4:0]]; note 1 I PORT OUTPUT FORMATS AND CONFIGURATION Dword formatting Dword formatting ...
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Philips Semiconductors PC-CODEC Table 218 Horizontal input window length; register set A [96H[7:0]; 97H[3:0]] and B [C6H[7:0]; C7H[3:0]] HORIZONTAL INPUT ACQUISITION WINDOW DEFINITION INPUT WINDOW LENGTH IN X (HORIZONTAL) (1) DIRECTION No output Odd lengths are allowed, but will be ...
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Philips Semiconductors PC-CODEC 18.2.5.8 Subaddresses 9CH to 9FH Table 221 Horizontal output window length; register set A [9CH[7:0]; 9DH[3:0]] and B [CCH[7:0]; CDH[3:0]] HORIZONTAL OUTPUT ACQUISITION WINDOW DEFINITION NUMBER OF DESIRED OUTPUT PIXEL IN X (HORIZONTAL) DIRECTION No output Odd ...
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Philips Semiconductors PC-CODEC Table 224 Accumulation length; register set A [A1H[5:0]] and B [D1H[5:0]] HORIZONTAL PRESCALER ACCUMULATION SEQUENCE LENGTH (XACL) Accumulation length = 1 Accumulation length = 2 ... Accumulation length = 64 Table 225 Prescaler DC gain and FIR ...
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Philips Semiconductors PC-CODEC 18.2.5.10 Subaddresses A4H to A6H Table 227 Luminance brightness control; register set A [A4H[7:0]] and B [D4H[7:0]] LUMINANCE BRIGHTNESS CONTROL Value = 0 Nominal value = 128 Value = 255 Table 228 Luminance contrast control; register set ...
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Philips Semiconductors PC-CODEC Table 231 Horizontal luminance phase offset; register set A [AAH[7:0]] and B [DAH[7:0]] HORIZONTAL LUMINANCE PHASE OFFSET Offset = 0 1 Offset = pixel 32 32 Offset = = 1 pixel 32 255 Offset = pixel 32 ...
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Philips Semiconductors PC-CODEC Table 235 Vertical chrominance scaling increment; register set A [B2H[7:0]; B3H[7:0]] and B [E2H[7:0]; E3H[7:0]] VERTICAL CHROMINANCE SCALING INCREMENT This value must be set to the luminance value YSCY[15:0] Table 236 Vertical scaling mode control; register set ...
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Philips Semiconductors PC-CODEC 19 PROGRAMMING START SET-UP OF DIGITAL VIDEO DECODER PART 19.1 Decoder part The given values force the following behaviour of the SAA7108E; SAA7109E decoder part: The analog input AI11 expects an NTSC M, PAL ...
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Philips Semiconductors PC-CODEC SUB REGISTER ADDRESS FUNCTION (HEX signal control 13 RT/X port output control 14 analog/ADC/compatibility control 15 VGATE start, FID change VSTA7 to VSTA0 16 VGATE stop 17 miscellaneous, VGATE configuration and MSBs 18 raw data ...
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Philips Semiconductors PC-CODEC 19.2 Audio clock generation part The given values force the following behaviour of the SAA7108E; SAA7109E audio clock generation part: Used crystal is 24.576 MHz Expected field frequency is 59.94 Hz (e.g. NTSC M standard) Generated audio ...
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Philips Semiconductors PC-CODEC 19.3 Data slicer and data type control part The given values force the following behaviour of the SAA7108E; SAA7109E VBI data slicer part: Closed captioning data is expected at line 21 of field 1 (60 Hz/525 line ...
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Philips Semiconductors PC-CODEC 19.4 Scaler and interfaces Table 242 shows some examples for the scaler programming where: prsc = prescale ratio fisc = fine scale ratio vsc = vertical scale ratio. number of input pixel The ratio is defined as: ...
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Philips Semiconductors PC-CODEC Table 243 Scaler and interface configuration examples 2 I C-BUS ADDRESS MAIN FUNCTION (HEX) Global settings 80 task enable, IDQ and back-end clock definition 83 XCLK output phase and X port output enable 84 IGPH, IGPV, IGP0 ...
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Philips Semiconductors PC-CODEC 2 I C-BUS ADDRESS MAIN FUNCTION (HEX) Horizontal phase scaling A8 horizontal scaling increment for luminance A9 AA horizontal phase offset luminance AC horizontal scaling increment for chrominance AD AE horizontal phase offset chrominance Vertical scaling B0 ...
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Philips Semiconductors PC-CODEC 20 PACKAGE OUTLINE BGA156: plastic ball grid array package; 156 balls; body 1.15 mm ball A1 index area ...
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Philips Semiconductors PC-CODEC 21 SOLDERING 21.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit ...
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Philips Semiconductors PC-CODEC 21.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE (3) BGA, HTSSON..T , LBGA, LFBGA, SQFP, SSOP..T USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS ...
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Philips Semiconductors PC-CODEC 22 DATA SHEET STATUS DATA SHEET PRODUCT LEVEL (1) STATUS STATUS I Objective data Development II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing ...