SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 135
SAA7109EEB
Manufacturer Part Number
SAA7109EEB
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7109EEB.pdf
(202 pages)
Specifications of SAA7109EEB
Lead Free Status / Rohs Status
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Philips Semiconductors
Table 115 Subaddresses 81H to 83H
Table 116 Subaddresses 90H and 94H
Table 117 Subaddresses 91H and 94H
Table 118 Subaddresses 92H and 94H
Table 119 Subaddresses 93H and 94H
Table 120 Subaddresses 95H and 96H
Table 121 Subaddress 96H
2004 Mar 16
PCL
XOFS
XPIX
YOFSO
YOFSE
YPIX
EFS
PCBN
SLAVE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
PC-CODEC
defines the frequency of the synthesized pixel clock PIXCLKO;
640
horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE
f
PIXCLK
LOGIC
LEVEL
480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
0
1
0
1
0
1
=
PCL
---------- -
2
24
frame sync signal at pin FSVGC ignored in slave mode
frame sync signal at pin FSVGC accepted in slave mode
normal polarity of CBO signal (HIGH during active video)
inverted polarity of CBO signal (LOW during active video)
the SAA7108E; SAA7109E is timing master to the graphics controller
the SAA7108E; SAA7109E is timing slave to the graphics controller
f
XTAL
8
; f
XTAL
= 27 MHz nominal, e.g. 640
135
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
YOFSO
DESCRIPTION
SAA7108E; SAA7109E
480 to NTSC M: PCL = 20F63BH;
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