SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 132

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
Table 99 Subaddress 6DH
Table 100 Subaddress 6EH
Table 101 Logic levels and function of PHRES
Table 102 Logic levels and function of LDEL
Table 103 Logic levels and function of FLC
2004 Mar 16
VTRIG
BLCKON
PHRES
LDEL
FLC
DATA BYTE
DATA BYTE
PC-CODEC
PHRES1
LDEL1
FLC1
0
0
1
1
0
0
1
1
0
0
1
1
DATA BYTE
DATA BYTE
DATA BYTE
sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
PHRES0
LOGIC
LEVEL
LDEL0
FLC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
encoder in normal operation mode; default after reset
output signal is forced to blanking level
selects the phase reset mode of the colour subcarrier generator; see Table 101
selects the delay on luminance path with reference to chrominance path;
see Table 102
field length control; see Table 103
no subcarrier reset
subcarrier reset every two lines
subcarrier reset every eight fields
subcarrier reset every four fields
no luminance delay; default after reset
1 LLC luminance delay
2 LLC luminance delay
3 LLC luminance delay
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
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DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAA7108E; SAA7109E
Product specification