SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 161
SAA7109EEB
Manufacturer Part Number
SAA7109EEB
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7109EEB.pdf
(202 pages)
Specifications of SAA7109EEB
Lead Free Status / Rohs Status
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Philips Semiconductors
18.2.2.19 Subaddress 12H
Table 167 RT signal control: RTS0 output; 12H[3:0]
The polarity of any signal on RTS0 can be inverted via RTP0[11H[3]].
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
2004 Mar 16
3-state
Constant LOW
CREF (13.5 MHz toggling pulse; see Fig.31)
CREF2 (6.75 MHz toggling pulse; see Fig.31)
HL; horizontal lock indicator (note 1):
VL; vertical and horizontal lock:
DL; vertical and horizontal lock and colour detected:
Reserved
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active line.
HREF is also generated during the vertical blanking interval (see Fig.31).
HS:
HQ; HREF gated with VGATE
Reserved
V123; vertical sync (see vertical timing diagrams Figs 29 and 30)
VGATE; programmable via VSTA[8:0] 17H[0] 15H[7:0], VSTO[8:0] 17H[1]
16H[7:0] and VGPS[17H[2]]
LSBs of the 9-bit ADC’s
FID; position programmable via VSTA[8:0] 17H[0] 15H[7:0];
see vertical timing diagrams Figs 29 and 30
PC-CODEC
HL = 0: unlocked
HL = 1: locked
VL = 0: unlocked
VL = 1: locked
DL = 0: unlocked
DL = 1: locked
programmable width in LLC8 steps via HSB[7:0] 06H[7:0] and HSS[7:0]
07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0] 11H[5:4]; see Fig.31
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
RTS0 OUTPUT
161
RTSE03 RTSE02 RTSE01 RTSE00
SAA7108E; SAA7109E
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Product specification
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
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