SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 75

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
Remark: Due to bandwidth considerations XPSC[5:0] and
XACL[5:0] can be chosen differently to the previously
mentioned equations or Table 41, as the horizontal phase
scaling is able to scale in the range from zooming up by
factor 3 to downscaling by a factor of
Figs 34 and 35 show some frequency characteristics of
the prescaler.
Table 41 shows the recommended prescaler
programming. Other programming, than given in Table 41,
may result in better alias suppression, but the resulting
DC gain amplification needs to be compensated by the
BCS control, according to the equation:
Where:
Table 40 FIR prefilter functions
2004 Mar 16
CONT[7:0]
2
DC gain = (XC2_1 + 1)
PC-CODEC
XDCG[2:0]
PFUV[1:0] A2H[7:6]
PFY[1:0] A2H[5:4]
=
DC gain
SATN[7:0]
00
01
10
11
=
XACL[5:0] + (1
lower integer of
1024
8191
--------------------------------- -
DC gain 64
XC2_1).
.
2
XDCG[2:0]
LUMINANCE FILTER
1 1 1.75 4.5 1.75 1 1
COEFFICIENTS
bypassed
1 2 2 2 1
1 2 1
75
For example, if XACL[5:0] = 5, XC2_1 = 1, then
DC gain = 10 and the required XDCG[2:0] = 4.
The horizontal source acquisition timing and the
prescaling ratio is identical for both the luminance and
chrominance path, but the FIR filter settings can be
defined differently in the two channels.
Fade-in and fade-out of the filters is achieved by copying
an original source sample each as first and last pixel after
prescaling.
Figs 32 and 33 show the frequency characteristics of the
selectable FIR filters.
SAA7108E; SAA7109E
CHROMINANCE COEFFICIENTS
3 8 10 8 3
bypassed
1 2 2 2 1
1 2 1
Product specification