SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 69

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
9.3
The High Performance video Scaler (HPS) is based on the
system as implemented in the SAA7140, but enhanced in
some aspects. Vertical upsampling is supported and the
processing pipeline buffer capacity is enhanced, to allow
more flexible video stream timing at the image port,
discontinuous transfers and handshake. The internal data
flow from block to block is discontinuous dynamically, due
to the scaling process.
The flow is controlled by internal data valid and data
request flags (internal handshake signalling) between the
sub-blocks. Therefore the entire scaler acts as a pipeline
buffer. Depending on the actually programmed scaling
parameters the effective buffer can exceed to an entire
line. The access/bandwidth requirements to the VGA
frame buffer are reduced significantly.
The high performance video scaler in the SAA7108E;
SAA7109E has the following major blocks.
2004 Mar 16
Acquisition control (horizontal and vertical timer) and
task handling (the region/field/frame based processing)
Prescaler, for horizontal downscaling by an integer
factor, combined with appropriate band limiting filters,
especially anti-aliasing for CIF format
Brightness, saturation and contrast control for scaled
output data
Line buffer, with asynchronous read and write, to
support vertical upscaling (e.g. for videophone
application, converting 240 into 288 lines, Y-C
4 : 2 : 2)
Vertical scaling, with phase accurate Linear Phase
Interpolation (LPI) for zoom and downscaling, or phase
accurate Accumulation Mode (ACM) for large
downscaling ratios and better anti-alias suppression
Variable Phase Delay (VPD), operates as horizontal
phase accurate interpolation for arbitrary non-integer
scaling ratios, supporting conversion between square
and rectangular pixel sampling
Output formatter for scaled Y-C
Y-C
FIFO, 32-bit wide, with 64 pixel capacity in Y-C
formats
Output interface, 8 or 16-bit (only if extended by H port)
data pins wide, synchronous or asynchronous
operation, with stream events on discrete pins, or coded
in the data stream.
PC-CODEC
B
Scaler
-C
R
4 : 1 : 1 and Y only (format also for raw data)
B
-C
R
4 : 2 : 2,
B
B
-C
-C
R
R
69
The overall H and V zooming (HV_zoom) is restricted by
the input/output data rate relationships. With a safety
margin of 2% for running in and running out, the maximum
HV_zoom is equal to:
For example:
1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit
2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit
The video scaler receives its input signal from the video
decoder or from the expansion port (X port). It gets 16-bit
Y-C
13.5 MHz from the decoder. A discontinuous data stream
can be accepted from the expansion port, normally 8-bit
wide ITU 656 like Y-C
qualifier on XDQ.
The input data stream is sorted into two data paths, one for
luminance (or raw samples), and one for time multiplexed
chrominance C
input format is converted to 4 : 2 : 2 for the horizontal
prescaling and vertical filter scaling operation.
The scaler operation is defined by two programming pages
A and B, representing two different tasks that can be
applied field alternating or to define two regions in a field
(e.g. with different scaling range, factors, and signal
source during odd and even fields).
Each programming page contains control for:
Raw VBI data will be handled as specific input format and
need its own programming page (equals own task).
0.98
Signal source selection and formats
Task handling and trigger conditions
Input and output acquisition window definition
H prescaler, V scaler and H phase scaling.
data at 13.5 MHz data rate, 1 cycle per pixel; output:
8-bit data at 27 MHz, 2 cycles per pixel; the maximum
HV_zoom is equal to:
data at 27 MHz data rate (ITU 656), 2 cycles per pixel;
output via I + H port: 16-bit data at 27 MHz clock,
1 cycle per pixel; the maximum HV_zoom is equal to:
B
0.98
0.98
-C
------------------------------------------------------------------------------------------------------------------------------------- -
in_pixel in_lines out_cycle_per_pix T_out_clk
R
4 : 2 : 2 input data at a continuous rate of
--------------------------------------------------------
720 288 2 37 ns
16.666 ms 22 64 s
------------------------------------------------------------- -
20 ms 24 64 s
720
B
and C
T_input_field T_v_blanking
240 1 37 ns
–
SAA7108E; SAA7109E
B
–
-C
R
samples. A Y-C
R
data, accompanied by a pixel
–
=
1.18
=
Product specification
2.34
B
-C
R
4 : 1 : 1