SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 150
SAA7109EEB
Manufacturer Part Number
SAA7109EEB
Description
Manufacturer
NXP Semiconductors
Datasheet
1.SAA7109EEB.pdf
(202 pages)
Specifications of SAA7109EEB
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Note
1. All unused control bits must be programmed with logic 0 to ensure compatibility to future enhancements.
18.2.2
18.2.2.1
Table 149 Chip version (CV) identification; 00H[7:4]; read only register
18.2.2.2
The programming of the horizontal increment delay is used to match internal processing delays to the delay of the ADC. Use recommended position
only.
Table 150 Horizontal increment delay; 01H[3:0]
Vertical luminance phase
offset ‘00’
Vertical luminance phase
offset ‘01’
Vertical luminance phase
offset ‘10’
Vertical luminance phase
offset ‘11’
Chip Version (CV)
No update
Minimum delay
Recommended position
Maximum delay
REGISTER FUNCTION
I
2
C-
Subaddress 00H
Subaddress 01H
BUS DETAIL
FUNCTION
FUNCTION
ADDR.
(HEX)
SUB
EC
ED
EE
EF
YPY07
YPY17
YPY27
YPY37
D7
YPY06
YPY16
YPY26
YPY36
D6
IDEL3
CV3
ID7
1
1
1
0
YPY05
YPY15
YPY25
YPY35
D5
YPY04
YPY14
YPY24
YPY34
D4
IDEL2
CV2
ID6
1
1
0
0
LOGIC LEVELS
YPY03
YPY13
YPY23
YPY33
D3
IDEL1
CV1
YPY02
YPY12
YPY22
YPY32
ID5
1
1
0
0
D2
YPY01
YPY11
YPY21
YPY31
D1
IDEL0
CV0
ID4
1
0
0
0
YPY00
YPY10
YPY20
YPY30
D0
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