SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 177

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
Table 203 I port I/O enable, output clock and gated clock phase control; global set 87H[7:4]; note 1
Notes
1. X = don’t care.
2. IPCK3 and IPCK2 only affects the gated clock (subaddress 80H, bit ICKS2 = 1).
Table 204 I port I/O enable, output clock and gated clock phase control; global set 87H[1:0]
2004 Mar 16
ICLK default output phase
ICLK phase shifted by
and ICKS0 = 0 (subaddress 80H)
ICLK phase shifted by about 3 ns
ICLK phase shifted by
3 ns
IDQ = gated clock default output phase
IDQ = gated clock phase shifted by
for gated clock output
IDQ = gated clock phase shifted by approximately 3 ns
IDQ = gated clock phase shifted by
3 ns
I port output is disabled by software
I port output is enabled by software
I port output is enabled by pin ITRI at logic 0
I port output is enabled by pin ITRI at logic 1
PC-CODEC
OUTPUT CLOCK AND GATED CLOCK PHASE CONTROL
alternatively to setting ‘01’
alternatively to setting ‘01’
1
1
2
2
I PORT I/O ENABLE
clock cycle
clock cycle + approximately
1
1
2
2
clock cycle
clock cycle + approximately
recommended for ICKS1 = 1
recommended
177
IPCK3
X
X
X
X
0
0
1
1
(2)
IPE1
SAA7108E; SAA7109E
CONTROL BITS 1 AND 0
0
0
1
1
CONTROL BITS 7 TO 4
IPCK2
X
X
X
X
0
1
0
1
(2)
IPCK1
Product specification
X
X
X
X
0
0
1
1
IPE0
0
1
0
1
IPCK0
X
X
X
X
0
1
0
1