SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 86

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
9.5.2
The video FIFO at the scaler output contains 32 Dwords.
That corresponds to 64 pixels in 16-bit Y-C
format. But as the entire scaler can act as a pipeline buffer,
the actually available buffer capacity for the image port is
much higher, and can exceed beyond a video line.
The image port and the video FIFO, can operate with the
video source clock (synchronous mode) or with an
externally provided clock (asynchronous, and burst mode),
as appropriate for the VGA controller or attached frame
buffer.
The video FIFO provides 4 internal flags, which report to
what extent the FIFO is actually filled. These are:
The trigger levels for FAE and FAF are programmable by
FFL[1:0] 86H[3:2] (16, 24, 28, full) and FEL[1:0] 86H[1:0]
(16, 8, 4, empty).
The state of this flag can be seen on pins IGP0 or IGP1.
The pin mapping is defined by subaddresses 84H
and 85H; see Section 10.5.
9.5.3
The data of the terminal VBI data slicer is collected in the
text FIFO before transmission over the I port is requested
(normally before the video window starts) and partitioned
into two FIFO sections. A complete line is fed into the FIFO
before a data transfer is requested. So normally, one line
of text data is ready for transfer while the next text line is
collected. Thus sliced text data is delivered as a block of
qualified data, without any qualification gaps in the byte
stream of the I port.
2004 Mar 16
The FIFO Almost Empty (FAE) flag
The FIFO combined flag (FCF) or FIFO filled, which is
set at almost full level and reset, with hysteresis, only
after the level crosses below the almost empty mark
The FIFO Almost Full (FAF) flag
The FIFO Overflow (FOVL) flag.
PC-CODEC
V
T
EXT
IDEO
FIFO
FIFO (
SUBADDRESS
86H)
B
-C
R
4 : 2 : 2
86
The decoded VBI data is collected in the dedicated VBI
data FIFO. Once the capture of a line is completed, the
FIFO can be streamed through the image port, preceded
by a header, giving the line number and standard.
The VBI data period can be signalled via the sliced data
flag on pin IGP0 or IGP1. The decoded VBI data is lead by
the ITU ancillary data header (DID[5:0] 5DH[5:0] at value
<3EH) or by SAV/EAV codes selected by DID[5:0] at value
3EH or 3FH. IGP0 or IGP1 is set if the first byte of the ANC
header is valid on the I port bus; it is reset if an SAV
occurs. Therefore it may frame multiple lines of text data
output, in case the video processing starts with a distance
of several video lines to the region of text data. Valid sliced
data from the text FIFO is available on the I port as long as
the IGP0 or IGP1 flag is set and the data qualifier is active
on pin IDQ.
The decoded VBI data is presented in two different data
formats, controlled by bit RECODE.
9.5.4
Sliced text data and scaled video data are transferred over
the same bus, the I port. The mixed transfer is controlled
by an arbitration circuit. If the video data is transferred
without any interrupt and the video FIFO does not need to
buffer any output pixel, the text data is inserted after the
end of a scaled video line, normally during the video
blanking interval.
RECODE = 1: values 00H and FFH will be recoded to
even parity values 03H and FCH
RECODE = 0: values 00H and FFH may occur in the
data stream as detected.
V
IDEO AND TEXT ARBITRATION
SAA7108E; SAA7109E
Product specification
(
SUBADDRESS
86H)