SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 163

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
18.2.2.20 Subaddress 13H
Table 169 RT/X port output control; 13H[7:0]
2004 Mar 16
5 and 4 X port XRV output
2 to 0
PC-CODEC
BIT
7
6
3
RTCO output enable
X port XRH output
selection
selection
horizontal lock indicator
selection
XPD7 to XPD0 (port
output format selection);
see Section 10.4
DESCRIPTION
OFTS[2:0]
XRVS[1:0]
SYMBOL
HLSEL
XRHS
RTCE
VALUE
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
0
1
163
3-state
enabled
HREF (see Fig.31)
HS:
V123; see Figs 29 and 30
ITU 656 related field ID; see Figs 29 and 30
inverted V123
inverted ITU 656 related field ID
copy of inverted HLCK status bit (default)
fast horizontal lock indicator (for special applications only)
ITU 656
ITU 656 like format with modified field blanking according
to VGATE position (programmable via VSTA[8:0] 17H[0]
15H[7:0], VSTO[8:0] 17H[1] 16H[7:0] and VGPS[17H[2]])
Y-C
reserved
multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0
multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0
reserved
multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0
programmable width in LLC8 steps via HSB[7:0] 06H[7:0]
and HSS[7:0] 07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0]
11H[5:4] (see Fig.31)
B
-C
R
4 : 2 : 2 8-bit format (no SAV/EAV codes inserted)
SAA7108E; SAA7109E
FUNCTION
Product specification