SAA7109EEB NXP Semiconductors, SAA7109EEB Datasheet - Page 136

• Manufacturer Part Number: SAA7109EEB
• Manufacturer: NXP Semiconductors

Specifications of SAA7109EEB

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Philips Semiconductors
Table 122 Subaddress 97H
Table 123 Subaddresses 98H and 99H
2004 Mar 16
ILC
YFIL
HSL
HFS
VFS
OFS
PFS
OVS
PVS
OHS
PHS
HLEN
DATA BYTE
DATA BYTE
DATA BYTE
PC-CODEC
horizontal length;
LOGIC
LEVEL
LOGIC
LEVEL
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
if hardware cursor insertion is active, set LOW for non-interlaced input signals
if hardware cursor insertion is active, set HIGH for interlaced input signals
luminance sharpness booster disabled
luminance sharpness booster enabled
normal trigger event handling of the horizontal state machine, if the SAA7108E;
SAA7109E is slave to HSVGC input
trigger event for horizontal state machine is shifted 128 PIXCLKs in advance, adapted
to a late HSVGC in slave mode
horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
pin FSVGC is switched to input
pin FSVGC is switched to active output
polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
pin VSVGC is switched to input
pin VSVGC is switched to active output
polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
pin HSVGC is switched to input
pin HSVGC is switched to active output
polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
HLEN
=
number of PIXCLKs
---------------------------------------------------- - 1
line
136
DESCRIPTION
–
DESCRIPTION
DESCRIPTION
SAA7108E; SAA7109E
Product specification