MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 107

MC68HC912B32VFU8

Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68HC912B32VFU8

Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
8.6 Erasing the FLASH EEPROM
This sequence demonstrates the recommended procedure for erasing the FLASH EEPROM. The V
voltage must be at the proper level prior to executing step 4 the first time.
The flowchart in
Freescale Semiconductor
10. If all of the FLASH EEPROM locations are erased, repeat the same number of pulses as required
11. Read the entire array to ensure that the FLASH EEPROM is erased.
12. Clear LAT.
13. Turn off V
1. Turn on V
2. Set the LAT bit and ERAS bit to configure the FLASH EEPROM for erasing.
3. Write to any valid address in the FLASH array. This allows the erase voltage to be turned on; the
4. Apply erase voltage by setting ENPE.
5. Delay for a single erase pulse, t
6. Remove erase voltage by clearing ENPE.
7. Delay while high voltage is turning off, t
8. Read the entire array to ensure that the FLASH EEPROM is erased.
9. If all of the FLASH EEPROM locations are not erased, repeat steps 4 through 7 until either the
data written and the address written are not important. The boot block will be erased only if the
control bit BOOTP is negated.
remaining locations are erased or until the maximum erase pulses have been applied, n
to erase the array. This provides 100 percent erase margin.
FP
FP
Figure 8-6
. Apply program/erase voltage to the V
. Reduce voltage on V
demonstrates the recommended erase sequence.
M68HC12B Family Data Sheet, Rev. 9.1
EPULSE
FP
pin to V
.
VERASE
DD
.
.
FP
pin.
Erasing the FLASH EEPROM
EP
.
FP
pin
107

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