MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 43

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Addr.
$004C
$004D
$0046
$0047
$0048
$0049
$004A
$004B
$004E
$004F
$0050
$0051
Notes:
1. Available only on MC68HC912B32 and MC68HC912BC32 devices.
2. Available only on MC68HC912B32 and MC68HC12BE32 devices.
3. Available only on MC68HC(9)12BC32 devices.
PWM Scale Register 1 (PWSCAL1)
PWM Channel Counter Register 0
PWM Channel Counter Register 1
PWM Channel Counter Register 2
PWM Channel Counter Register 3
PWM Channel Period Register 0
PWM Channel Period Register 1
PWM Channel Period Register 2
PWM Channel Period Register 3
PWM Scale Counter Register 1
PWM Channel Duty Register 0
PWM Channel Duty Register 1
Register Name
See page 132.
See page 132.
See page 133.
See page 133.
See page 133.
See page 133.
See page 134.
See page 134.
See page 134.
See page 134.
See page 135.
See page 135.
(PWSCNT1)
(PWCNT0)
(PWCNT1)
(PWCNT2)
(PWCNT3)
(PWPER0)
(PWPER1)
(PWPER2)
(PWPER3)
(PWDTY0)
(PWDTY1)
Figure 2-1. Register Map (Sheet 4 of 19)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
M68HC12B Family Data Sheet, Rev. 9.1
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
Bit 7
0
0
0
0
0
0
1
1
1
1
1
1
= Unimplemented
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
Bit 6
6
0
0
0
0
0
0
1
1
1
1
1
1
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
Bit 5
5
0
0
0
0
0
0
1
1
1
1
1
1
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
Bit 4
R
4
0
0
0
0
0
0
1
1
1
1
1
1
= Reserved
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
Bit 3
3
0
0
0
0
0
0
1
1
1
1
1
1
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
Bit 2
2
0
0
0
0
0
0
1
1
1
1
1
1
U = Unaffected
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
Bit 1
1
0
0
0
0
0
0
1
1
1
1
1
1
Registers
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
Bit 0
0
0
0
0
0
0
1
1
1
1
1
1
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