MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 268

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

16.12.6 msCAN12 Receiver Interrupt Enable Register
WUPIE — Wakeup Interrupt Enable Bit
RWRNIE — Receiver Warning Interrupt Enable Bit
TWRNIE — Transmitter Warning Interrupt Enable Bit
RERRIE — Receiver Error Passive Interrupt Enable Bit
TERRIE — Transmitter Error Passive Interrupt Enable Bit
BOFFIE — Bus-Off Interrupt Enable Bit
OVRIE — Overrun Interrupt Enable Bit
RXFIE — Receiver Full Interrupt Enable Bit
268
msCAN12 Controller
0 = No interrupt is generated from this event.
1 = A wakeup event results in a wakeup interrupt.
0 = No interrupt is generated from this event.
1 = A receiver warning status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter warning status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receiver error passive status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A transmitter error passive status event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A bus-off event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = An overrun event results in an error interrupt.
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event results in a receive interrupt.
Address: $0105
The CRIER register is held in the reset state when the SFTRES bit in
CMCR0 is set.
Reset:
Figure 16-21. msCAN12 Receiver Interrupt Enable Register (CRIER)
Read:
Write:
WUPIE
Bit 7
0
RWRNIE
6
0
M68HC12B Family Data Sheet, Rev. 9.1
TWRNIE
5
0
NOTE
RERRIE
4
0
TERRIE
3
0
BOFFIE
2
0
OVRIE
1
0
Freescale Semiconductor
RXFIE
Bit 0
0