MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 89

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

PE1 and PE0 are associated with XIRQ and IRQ and cannot be configured as outputs. These pins can
be read regardless of whether the alternate interrupt functions are enabled.
This register is not in the map in peripheral mode and expanded modes while the EME control bit is set.
6.3.7 Port E Assignment Register
Read: Anytime, if register is in the map
Write: Varies from bit to bit, if register is in the map
The PEAR register is used to choose between the general-purpose I/O functions and the alternate bus
control functions of port E. When an alternate control function is selected, the associated DDRE bits are
overridden.
The reset condition of this register depends on the mode of operation because bus-control signals are
needed immediately after reset in some modes.
In normal single-chip mode, no external bus control signals are needed, so all of port E is configured for
general-purpose I/O.
In special single-chip mode, the E clock is enabled as a timing reference, and the other bits of port E are
configured for general-purpose I/O.
In normal expanded modes, the reset vector is located in external memory. The E clock may be required
for this access but R/W is only needed by the system when there are external writable resources.
Therefore, in normal expanded modes, only the E clock is configured for its alternate bus control function
and the other bits of port E are configured for general-purpose I/O. If the normal expanded system needs
any other bus-control signals, PEAR would need to be written before any access that needed the
additional signals.
In special expanded modes, IPIPE1, IPIPE0, E, R/W, and LSTRB are configured as bus-control signals.
In peripheral mode, the PEAR register is not accessible for reads or writes.
NDBE — No Data Bus Enable Bit
Freescale Semiconductor
Normal: Write once
Special: Write anytime except the first time
1 = PE7 used for general-purpose I/O
0 = PE7 used for external control of data enables on memories
Special single-chip:
Normal single-chip:
Special expanded:
Normal expanded:
Reset states:
Peripheral:
Address: $000A
Read:
Write:
NDBE
Bit 7
Figure 6-7. Port E Assignment Register (PEAR)
1
0
0
0
1
= Unimplemented
CGMTE
M68HC12B Family Data Sheet, Rev. 9.1
6
0
0
0
0
1
PIPOE
5
0
1
0
1
0
NECLK
4
1
0
0
0
1
LSTRE
3
0
1
0
1
0
RDWE
2
0
1
0
1
0
1
0
0
0
0
0
0
Bit 0
0
0
0
0
0
0
Registers
89