MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 181

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

13.4.16 Input Control Pulse Accumulators Control Register
Read: Anytime
Write: Anytime
The 8-bit pulse accumulators, PAC3 and PAC2, can be enabled only if PAEN in PATCL ($A0) is cleared.
If PAEN is set, PA3EN and PA2EN have no effect. The 8-bit pulse accumulators, PAC1 and PAC0, can
be enabled only if PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN have no effect.
PAxEN — 8-Bit Pulse Accumulator x Enable Bits
13.4.17 Delay Counter Control Register
Read: Anytime
Write: Anytime
If enabled, after detection of a valid edge on input capture pin, the delay counter counts the pre-selected
number of P clock (module clock) cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of the level before the transition.This
will avoid reaction to narrow input pulses.
After counting, the counter will be cleared automatically. Delay between two active edges of the input
signal period should be longer than the selected counter delay.
DLYx — Delay Counter Select Bits
Freescale Semiconductor
0 = 8-bit pulse accumulator disabled
1 = 8-bit pulse accumulator enabled
Figure 13-37. Input Control Pulse Accumulators Control Register (ICPACR)
Address: $00A8
Address: $00A9
Reset:
Reset:
Read:
Read:
Write:
Write:
Figure 13-38. Delay Counter Control Register (DLYCT)
Bit 7
Bit 7
0
0
0
0
DLY1
0
0
1
1
6
0
0
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
DLY0
5
0
0
5
0
0
0
1
0
1
4
0
0
4
0
0
Disabled (bypassed)
256 P clock cycles
512 P clock cycles
1024 P clock cycles
PA3EN
3
0
3
0
0
Delay
PA2EN
2
0
2
0
0
PA1EN
DLY1
1
0
1
0
PA0EN
DLY0
Bit 0
Bit 0
0
0
Timer Registers
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