MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 160

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Enhanced Capture Timer (ECT) Module
The 16-bit modulus down-counter can control the transfer of the IC register’s contents and the pulse
accumulators to the respective holding registers for a given period, every time the count reaches 0. The
modulus down-counter can also be used as a stand-alone timebase with periodic interrupt capability.
13.3.1 IC Channels
The IC channels are composed of four standard IC registers and four buffered IC channels.
13.3.1.1 Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin transition.
This will prevent the captured value to be overwritten until it is read.
13.3.1.2 Buffered IC Channels
There are two modes of operations for the buffered IC channels.
IC Latch Mode (see
IC Queue Mode (see
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When enabled (LATQ = 1), the main timer value is memorized in the IC register by a valid input pin
transition. The value of the buffered IC register is latched to its holding register by the modulus counter
for a given period when the count reaches 0, by a write $0000 to the modulus counter or by a write to
ICLAT in the 16-bit modulus down-counter control register (MCCTL).
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When enabled (LATQ = 0), the main timer value is memorized in the IC register by a valid input pin
transition.
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In queue mode, reads of the holding register will latch the corresponding pulse accumulator value to
its holding register.
An IC register is empty when it has been read or latched into the holding register.
A holding register is empty when it has been read.
If the corresponding NOVWx bit of the input control overwrite register (ICOVW) is cleared, with a
new occurrence of a capture, the contents of IC register are overwritten by the new value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register cannot be written
unless it is empty.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the contents of IC register are overwritten by the new value. In case of latching, the
contents of its holding register are overwritten.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see
prevent the captured value to be overwritten until it is read or latched in the holding register.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the value of the IC register will be transferred to its holding register and the IC register
memorizes the new timer value.
If the corresponding NOVWx bit of the ICOVW register is set, the capture register or its holding
register cannot be written by an event unless they are empty (see
Figure
Figure
13-1):
13-2):
M68HC12B Family Data Sheet, Rev. 9.1
13.3.1 IC
13.3.1 IC
Channels). This will
Channels).
Freescale Semiconductor