MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 146

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Standard Timer (TIM)
Read: Anytime
Write: Anytime
EDGnB and EDGnA — Input Capture Edge Control Bits
12.3.7 Timer Interrupt Mask Registers
Read: Anytime
Write: Anytime
The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the
corresponding flag is disabled from causing a hardware interrupt. If set, the corresponding flag is enabled
to cause a hardware interrupt.
146
These 8 pairs of control bits configure the input capture edge detector circuits. See
Address: $008A
Address: $008B
Address: $008C
Reset:
Reset:
Reset:
Read:
Read:
Read:
Write:
Write:
Write:
EDGnB
0
0
1
1
EDG7B
EDG3B
Figure 12-12. Timer Interrupt Mask 1 Register (TMSK1)
Bit 7
Bit 7
Bit 7
C7I
0
0
0
Table 12-2. Edge Detector Circuit Configuration
Figure 12-10. Timer Control Register 3 (TCTL3)
Figure 12-11. Timer Control Register 4 (TCTL4)
EDGnA
EDG7A
EDG3A
0
1
0
1
C6I
6
0
6
0
6
0
M68HC12B Family Data Sheet, Rev. 9.1
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
EDG6B
EDG2B
C5I
5
0
5
0
5
0
EDG6A
EDG2A
C4I
4
0
4
0
4
0
Configuration
EDG5B
EDG1B
C3I
3
0
3
0
3
0
EDG5A
EDG1A
C2I
2
0
2
0
2
0
EDG4B
EDG0B
C1I
1
0
1
0
1
0
Freescale Semiconductor
EDG4A
EDG0A
Bit 0
Bit 0
Bit 0
Table
C0I
0
0
0
12-2.