MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 180

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Enhanced Capture Timer (ECT) Module
MCEN — Modulus Down-Counter Enable Bit
MCPR1 and MCPR0 — Modulus Counter Prescaler Select Bits
13.4.15 16-Bit Modulus Down-Counter Flag Register
Read: Anytime
Write: Only for clearing bit 7
MCZF — Modulus Counter Underflow Interrupt Flag
POLF3–POLF0 — First Input Capture Polarity Status Bits
180
When MCEN = 0, the counter is preset to $FFFF. This will prevent an early interrupt flag when the
modulus down-counter is enabled.
These two bits specify the division rate of the modulus counter prescaler. The newly selected prescaler
division rate will not be effective until a load of the load register into the modulus counter count register
occurs.
The flag is set when the modulus down-counter reaches $0000. Writing 1 to this bit clears the flag.
Writing 0 has no effect. Any access to the MCCNT register will clear the MCZF flag in this register when
TFFCA bit in register TSCR ($86) is set.
This are read-only bits. Writing to these bits has no effect. Each status bit gives the polarity of the first
edge which has caused an input capture to occur after capture latch has been read. Each POLFx
corresponds to a timer PORTx input.
0 = Modulus counter disabled.
1 = Modulus counter is enabled.
0 = The first input capture has been caused by a falling edge.
1 = The first input capture has been caused by a rising edge.
Address: $00A7
Reset:
Figure 13-36. 16-Bit Modulus Down-Counter Flag Register (MCFLG)
Read:
Write:
MCZF
Bit 7
0
MCPR1
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
0
0
1
1
5
0
0
MCPR0
0
1
0
1
4
0
0
Division Rate
POLF3
Prescalar
3
0
16
1
4
8
POLF2
2
0
POLF1
1
0
Freescale Semiconductor
POLF0
Bit 0
0