MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 241
MC68HC912B32VFU8
Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC912B32VFU8.pdf
(334 pages)
Specifications of MC68HC912B32VFU8
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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15.9.6 Port DLC Control Register
Read: Anytime
Write: Anytime
The BDLC port DLC functions as a general-purpose I/O port. BDLC functions takes precedence over the
general-purpose port when enabled.
BDLCEN — BDLC Enable Bit
PUPDLC — BDLC Pullup Enable Bit
RDPDLC — BDLC Reduced Drive Bit
Freescale Semiconductor
1 = Configure I/O pins for BDLC function. BDLC is active.
0 = Configure BDLC I/O pins as general-purpose I/O. BDLC is off.
1 = Connects internal pullups to PORTDLC I/O pins
0 = Disconnects internal pullups from PORTDLC I/O pins
1 = Configure PORTDLC I/O pins for reduced drive strength.
0 = Configure PORTDLC I/O pins for normal drive strength.
Address: $00FD
Reset:
Read:
Write:
Bit 7
0
0
Table 15-5. Offset Bit Values and Transceiver Delay
Figure 15-18. Port DLC Control Register (DLCSCR)
= Unimplemented
BO3–BO0
6
0
0
M68HC12B Family Data Sheet, Rev. 9.1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5
0
0
4
0
0
Expected Delay (µs)
3
0
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
BDLCEN
2
0
PUPDLC
1
0
RDPDLC
BDLC Registers
Bit 0
0
241
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