MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 21

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

1.3 Slow-Mode Clock Divider Advisory
Current versions of the M68HC12B-series devices include a slow-mode clock divider feature. This feature
is fully described in
located at $00E0. Older device mask sets do not support the slow-mode clock divider feature. This
register address is reserved in older devices and provides no function.
Mask sets that do not have the slow-mode clock divider feature on the MC68HC912B32 include: G96P,
G86W, and H91F.
Mask sets that do not have the slow-mode clock divider feature on the MC68HC12BE32 include: H54T
and J38M.
Mask sets that do not have the slow-mode clock divider feature on the MC68HC(9)12BC32 include: J15G.
Freescale Semiconductor
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Serial interfaces:
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Computer operating properly (COP) watchdog timer, clock monitor, and periodic interrupt timer
Slow-mode clock divider
80-pin quad flat pack (QFP)
Up to 63 general-purpose input/output (I/O) lines
Single-wire background debug mode (BDM)
On-chip hardware breakpoints
Asynchronous serial communications interface (SCI)
Synchronous serial peripheral interface (SPI)
J1850 byte data link communication (BDLC), MC68HC912B32 and MC68HC12BE32 only
Controller area network (CAN), MC68HC(9)12BC32 only
Chapter 10 Clock Generation Module
M68HC12B Family Data Sheet, Rev. 9.1
(CGM). The register that controls this feature is
Slow-Mode Clock Divider Advisory
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