MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 145
MC68HC912B32VFU8
Manufacturer Part Number
MC68HC912B32VFU8
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC912B32VFU8.pdf
(334 pages)
Specifications of MC68HC912B32VFU8
Cpu Family
HC12
Device Core Size
16b
Frequency (max)
8MHz
Interface Type
SCI/SPI
Program Memory Type
EPROM
Program Memory Size
32KB
Total Internal Ram Size
1KB
# I/os (max)
63
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC912B32VFU8
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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TSBCK — Timer Stops While in Background Mode Bit
TFFCA — Timer Fast Flag Clear All Bit
12.3.6 Timer Control Registers
Read: Anytime
Write: Anytime
OMn — Output mode
OLn — Output level
Freescale Semiconductor
These eight pairs of control bits are encoded to specify the output action to be taken as a result of a
successful OCn compare (see
becomes an output tied to OCn regardless of the state of the associated DDRT bit.
0 = Allows timer to continue running while in background mode
1 = Disables timer when MCU is in background mode; useful for emulation
0 = Allows timer flag clearing to function normally
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel
($90–$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any
access to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register
($A2 and $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1).
This has the advantage of eliminating software overhead in a separate clear sequence.
Address: $0088
Address: $0089
Extra care is required to avoid accidental flag clearing due to unintended
accesses.
Reset:
Reset:
Read:
Read:
Write:
Write:
OMn
0
0
1
1
OM7
OM3
Bit 7
Bit 7
0
0
Figure 12-8. Timer Control Register 1 (TCTL1)
Figure 12-9. Timer Control Register 2 (TCTL2)
Table 12-1. Compare Result Output Action
OL7
OL3
Table
OLn
6
0
6
0
0
1
0
1
M68HC12B Family Data Sheet, Rev. 9.1
12-1). When either OMn or OLn is 1, the pin associated with OCn
OM6
OM2
5
0
5
0
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to 0
Set OCn output line to 1
NOTE
OL6
OL2
4
0
4
0
OM5
OM1
3
0
3
0
Action
OL5
OL1
2
0
2
0
OM4
OM0
1
0
1
0
Bit 0
Bit 0
OL4
OL0
0
0
Block Diagram
145
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