MC68HC912B32VFU8 Freescale Semiconductor, MC68HC912B32VFU8 Datasheet - Page 77

• Manufacturer Part Number: MC68HC912B32VFU8
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC912B32VFU8

• Cpu Family: HC12
• Device Core Size: 16b
• Frequency (max): 8MHz
• Interface Type: SCI/SPI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 1KB
• # I/os (max): 63
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Internal Resource Mapping
5.2.2.4 Special Peripheral Mode
The CPU is not active in this mode. An external master can control on-chip peripherals for testing
purposes. It is not possible to change to or from this mode without going through reset. Background
debugging should not be used while the MCU is in special peripheral mode as internal bus conflicts
between BDM and the external master can cause improper operation of both modes.
5.2.3 Background Debug Mode
Background debug mode (BDM) is an auxiliary operating mode that is used for system development.
BDM is implemented in on-chip hardware and provides a full set of debug operations. Some BDM
commands can be executed while the CPU is operating normally. Other BDM commands are firmware
based and require the BDM firmware to be enabled and active for execution.
In special single-chip mode, BDM is enabled and active immediately out of reset. BDM is available in all
other operating modes, but must be enabled before it can be activated. BDM should not be used in special
peripheral mode because of potential bus conflicts.
Once enabled, background mode can be made active by a serial command sent via the BKGD pin or
execution of a CPU12 BGND instruction. While background mode is active, the CPU can interpret special
debugging commands, read and write CPU registers, peripheral registers, and locations in memory.
While BDM is active, the CPU executes code located in a small on-chip ROM mapped to addresses
$FF00 to $FFFF; BDM control registers are accessible at addresses $FF00 to $FF06. The BDM ROM
replaces the regular system vectors while BDM is active. While BDM is active, the user memory from
$FF00 to $FFFF is not in the map except through serial BDM commands.
BDM allows read and write access to internal memory-mapped registers and RAM and read access to
EEPROM, FLASH EEPROM, or ROM without interrupting the application code executing in the CPU. This
non-intrusive mode uses dead bus cycles to access the memory and in most cases will remain cycle
deterministic. Refer to
18.3 Background Debug Mode (BDM)
for more details.
5.3 Internal Resource Mapping
The internal register block, RAM, FLASH EEPROM/ROM, and EEPROM have default locations within the
64-Kbyte standard address space but may be reassigned to other locations during program execution by
setting bits in mapping registers INITRG, INITRM, and INITEE. During normal operating modes, these
registers can be written once. It is advisable to explicitly establish these resource locations during the
initialization phase of program execution, even if default values are chosen, to protect the registers from
inadvertent modification later.
Writes to the mapping registers go into effect between the cycle that follows the write and the cycle after
that. To assure that there are no unintended operations, a write to one of these registers should be
followed with a no operation (NOP) instruction.
If conflicts occur when mapping resources, the register block will take precedence over the other
resources; RAM, FLASH EEPROM/ROM, or EEPROM addresses occupied by the register block will not
be available for storage. When active, BDM ROM takes precedence over other resources, although a
conflict between BDM ROM and register space is not possible.
Table 5-2
shows resource mapping
precedence.
In expanded modes, all address space not utilized by internal resources is by default external memory.
M68HC12B Family Data Sheet, Rev. 9.1
Freescale Semiconductor
77