TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 109

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

Note: Since an interrupt is generated 80 times, the first read to internal RAM (which requires 1 additional state) occurs
Sample 1: Calculation example for CPU + HDMA
Conditions:
Calculation example:
Transfer count
80 times, requiring additional 80 states in total. In addition, from bus REQ to bus ACK, an overhead time of 2
states is also needed for each interrupt request, requiring additional 160 states in total.
follows:
16 (64 bytes/4 bytes = 16 times) and counter B is set to 80.
CPU operation speed (f
I
I
DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I
DMAC source data read time:
DMAC destination write time:
To transfer 5 Kbytes of data in 4-byte units, the transfer count is calculated as
5 Kbytes/4 bytes = 1280 [times]
Since I
t
HDMA start interval [s] = 1 / I
CPU bus stop rate = t
2
2
STOP
S sampling frequency
S data transfer bit length
Internal RAM data read time
= 1 state/4 bytes (However, the first 1 byte requires 2 states.)
I
2
S register write time = 2 states/4 bytes
(HDMA) = (((1 + 2) × 16) × 80) + 80 + 160) / f
2
S generates an interrupt for every 64 bytes, the DMAC’s counter A is set to
STOP
SYS
92CF29A-107
= 83.33 [ms]
= 68 [μs] / 83.33 [ms] = 0.08 [%]
)
(HDMA) [s] / HDMA start interval [s]
2
S sampling frequency [Hz] × (64 / 16 )
: 60 MHz
: 48 kHz (60 MHz/25/50 = 48 kHz)
: 16 bits
SYS
[s] = 68 [μs]
2
S
TMP92CF29A
2009-06-11