TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 512

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

Note: In case of I
(a) <SYSCKE0>
(b) <DTFMT01:00>
(c) <BIT0>
(d) <DIR0>
(e) <CNTE0>
(f) <TXE0>
(g) <CLKE0>
<CLKE0>= “1” with I
I
2
operating, for reduce the power consumption, we recommends to disable: <SYSCKE0>=
“0”.
the data format, set <SYSCKE0>= “1”, <CNTE0>=“0” and <TXE0>= “0”.
the data format, set <SYSCKE0>= “1”, <CNTE0>= “0” and <TXE0>= “0”.
the data format, set <SYSCKE0>= “1”, <CNTE0>=“0” and <TXE0>=“0”.
Clock generator counter will not clear by <TXE0>=“0” and <CNTE0>=“1”
Transmission is stopped by <TXE0>=“0”, started by <TXE0>=“1”.
during effective data out period.
S format.
This bit controls to connect source clock to I
In case of this circuit is operated, it must enable: <SYSCKE0>= “1”. And except
This bit controls data format: I
It is not possible to change data format during data transmission. Before changing
This bit controls data length: 8/16 bits.
It is not possible to change data length during data transmission. Before changing
This bit controls direction: LSB_Fast or MSB_Fast
It is not possible to change data direction during data transmission. Before changing
This bit controls clock generator counter: Clear/Start.
When this circuit is used, always set to the start condition.
Clock generator counter will clear by <TXE0>=“0” and <CNTE0>=“0”, However,
This bit controls data transmission and FIFO buffer clear: Trans/Stop and Clear
Output FIFO buffer is cleared by <TXE0>=“0”.
This bit controls CLK out period.
<CLKE0>=“0”: always out I2S0CKO clock, <CLKE0>=“1”: I2S0CKO clock out
2
S format, firstly I2S0WS signal change and after 1clock period, effective data out. If set to
2
S format, 1 clock pulse after I2S0WS don't out. It is not possible <CLKE0>=“0” setting with
92CF29A-510
2
S, right justify and left justify.
2
S circuit.
TMP92CF29A
2009-06-11