TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 516

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

I2S0C
(180AH)
(180BH)
bit Symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note: It is recommended that the value to be set in I2S0C<CK07:00> be an even number. Although it is possible to set
(3) Setting example for the clock generator (8-bit counter/6-bit counter)
an odd number, the clock duty of the CK signal does not become 50%. Setting an odd number causes the High
width of the I2S0CKO signal to become longer by one f
0, the Low width becomes longer than the High width.)
When f
follows:
and sampling frequency.
The clock generator generates the reference clock for setting the data transfer speed
•
CK07
<CLKS0>. An 8-bit counter is provided to divide the source clock by 3 to 256. (The
divider value cannot be set to 1 or 2.)
set to within 10 MHz by an appropriate combination of source clock frequency and
divider value.
15
8-bit counter set value
I2S0CKO = f
7
0
The transfer clock is generated by dividing the clock selected by I2S0CTL
The transfer clock must not exceed 10 MHz. Make sure that the transfer clock is
SYS
Setting the transfer clock I2S0CKO
00000000
00000001
11111111
= 60 MHz and I2S0C<CK07:00> = 150, the data transfer speed is set as
CK06
14
6
0
= 60 [MHz]/150 = 400 [kbps]
SYS
/150
WS05
CK05
Divider value for CK signal (8-bit counter)
13
5
0
0
92CF29A-514
WS04
CK04
Divider value for WS signal (6-bit counter)
12
4
0
0
R/W
SYS
WS03
or f
CK03
11
3
0
0
PLL
Divider value
256
1
255
pulse than the Low width. (When <EDGE0> =
R/W
WS02
CK02
10
2
0
0
WS01
CK01
1
9
0
0
TMP92CF29A
WS00
CK00
0
8
0
0
2009-06-11