TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 696

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

Symbol
PGFC
PMFC
PKFC
PKFC
PJCR
PJFC
PLFC
(1) I/O ports (6/11)
PORTG
function
register
PORTJ
control
register
PORTJ
function
register
PORTK
function
register
PORTL
control
register
PORTL
function
register
PORTM
function
register
Name
Address
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
(Prohibit
004EH
004FH
005BH
0043H
RMW)
RMW)
0053H
RMW)
0057H
RMW)
0057H
RMW)
RMW)
RMW)
0: Port
1: SDCKE
0: Port
1: LGOE2
0: Port
1: PWE
PM7F
PK7F
PL7C
PJ7F
PL7F
W
7
−
−
−
−
−
0
0
0
0
0
0: Port
1:NDCLE
0: Port
1: LGOE1
0:Input port
1:output
output
PL6FC
port,
NDCLE
output
PK6F
PJ6C
PL6F
PJ6F
6
0
−
0
−
0
−
0
−
0
−
92CF29A-694
W
0: Port
1:NDALE
0: Port
1: LGOE0
0:Input port
1:output
0: Port
output
port,
NDALE
output
PJ5C
PK5F
PL5C
PJ5F
PL5F
5
0
−
0
−
0
−
0
−
0
−
0: Port
1:SDLUDQM
0: Port
1: LHSYNC
0: Input
1: Data bus for LCDC (LD7~LD0)
PK4F
PL4C
PL4F
PJ4F
4
0
−
0
−
0
−
0
−
W
W
W
0:Input
1:
0: Port
1:SDLLDQM
0: Port
1: LVSYNC
1: Output
port,AN3
PG3F
ADTRG
PK3F
PL3C
PL3F
PJ3F
W
3
0
−
0
−
0
−
0
−
0
−
W
0: Port
1:
0: Port
1: LFR
0: Port
1:
MLDALM
<PM2>=1,
<PM2>=1
ALARM
SRWR
SDWE
PM2F
PK2F
PL2C
PJ2F
PL2F
2
0
−
0
−
0
−
0
−
0
−
at
at
,
W
0: Port
1:
0: Port
1:MLDALM
0: Port
1: LLOAD
TA1OUT
at <PM1>=0
at <PM1>=1
SRLUB
SDCAS
PM1F
PK1F
PL1C
PJ1F
PL1F
1
0
−
0
−
0
−
0
−
0
−
TMP92CF29A
,
2009-06-11
0: Port
1:
0: Port
1: LCP0
SRLLB
SDRAS
PK0F
PL0C
PL0F
PJ0F
0
0
−
0
−
0
−
0
−
,