TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 339

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

BR0CR
(1203H)
BR0ADD
(1204H)
0
1
+ (16 − K)/16 division enable
Bit symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
BR0ADD
<BR0K3:0>
Disable
Enable
Note1:Availability of +(16-K)/16 division function
Note2:Set BR0CR <BR0ADDE> to “1” after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when the +(16-K)/16
1111(K = 15)
0001(K = 1)
0000
Figure 3.15.12 Baud rate generator control (channel 0, BR0CR, BR0ADD)
The baud rate generator can be set to “1” in UART mode only when the +(16-K)/16 division function is not used.
Do not use in I/O interface mode.
division function is used. If the unused bits in the BR0ADD register is written, it does not affect operation. If that
bits is read, it becomes undefined.
to
BR0CR
<BR0S3:0>
Always
write “0”
Sets baud rate generator frequency divisor
2 to 15
1 , 16
7
7
−
0
N
0000(N = 16)
0001 (N = 1)
+ (16 − K)/16
division
0: Disable
1: Enable
BR0ADDE
BR0CR<BR0ADDE> = “1”
Disable
Disable
UART mode
or
6
0
6
○
×
00: φ T0
01: φ T2
10: φ T8
11: φ T32
00
01
10
11
BR0CK1
Setting the input clock of baud rate generator
1111 (N = 15)
N + (16-K) /16
0010 (N = 2)
Divided by
5
5
0
Disable
to
92CF29A-337
Internal clock φ T0
Internal clock φ T2
Internal clock φ T8
Internal clock φ T32
I/O mode
BR0CK0
4
4
0
×
×
BR0CR<BR0ADDE> = “0”
0001 (N = 1) (UART only)
R/W
1111(N = 15)
0000(N = 16)
Divided by N
to
BR0S3
BR0K3
3
0
3
0
(divided by N + (16-K) / 16)
Sets frequency divisor “K”
Divided frequency setting
BR0S2
BR0K2
2
0
2
0
R/W
BR0S1
BR0K1
1
0
1
0
TMP92CF29A
BR0S0
BR0K0
0
0
0
2009-06-11
0