TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 417

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TMP92xy29FG

Manufacturer Part Number
TMP92xy29FG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy29FG

Package
QFP176
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
98
Power Supply Voltage(v)
3.0 to 3.6
USBREADY
(07E6H)
VDD
INTXX
PortXX
(Pull-up on/off)
Write signal
bit Symbol
Read/Write
Reset State
3.17.3.27 USBREADY Register
USBREADY (Bit0)
Note1: External pull-up resistor and control switch are needed with the TMP92CF29A.
Note2: The above setting is an example for when communication. A specific circuit is required to prevent cullent flow
0: Writing to descriptor RAM has finished.
1: Writing to descriptor RAM is enabled.
(However, writing to descriptor RAM is prohibited when connected to host.)
at connector detection , no-use, and no connection.
case, UDC disable detecting USB_RESET signal until USBREADY register is written
“0” after release of USB_RESET.
resistor is connected to host in OFF condition, this condition is equivalent condition
with USB_RESET signal by pull-down resistor on the host side. Therefore UDC is not
detected in USB_RESET until “0” is written to USBREADY register
This register informs finishing writing data to descriptor RAM on UDC.
After assigned data to descriptor RAM, write “0” to bit0.
Detect level of VDD signal from USB cable, and execute initialize sequence. In this
If the pull-up resistor on D+ signal is controlled by control signal, when pull-up
7
USB host
GND
6
15 kΩ
15 kΩ
92CF29A-415
5
Descriptor RAM access
Device ID RAM
Register in USB
R1 = 1.5 kΩ
4
R2
R3
3
VCC
VSS
PortXX
D+
D−
USBREADY registera access
2
TMP92CF29A
CPU
UDC
TMP92CF29A
1
2009-06-11
USBREADY
R/W
0
0

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