TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 151

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

PFDR
(008FH)
PFFC
(003FH)
PFCR
(003EH)
PF
(003CH)
PF2 setting
<PF2F>
<PF2C>
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: A read-modify-write operation cannot be performed for the registers PFCR, PFFC.
Input port
0
I2S0WS output
0: Port
1: SDCLK
PF7D
PF7F
R/W
R/W
PF7
W
7
7
1
−
7
7
1
−
1
−
Output port
1
6
6
6
6
Figure 3.8.28 Register for Port F
PF1 setting
<PF1F>
Input/Output buffer drive register for standby mode
<PF1C>
0
1
Port F function register
Port F control register
Port F drive register
5
5
5
5
92CF29A-149
Port F register
Input port
0
I2S0DO output
4
4
4
4
Output port
1
3
3
3
3
PF0 setting
Data from external port (Output latch
<PF0F>
PF2D
PF2F
PF2C
PF2
<PF0C>
2
0
−
2
1
−
2
2
−
0
0
1
Refer to following table
Refer to following table
register is set to “1”)
Input port
PF1D
PF1F
R/W
PF1C
PF1
W
1
−
1
1
0
−
W
1
1
−
0
I2S0CKOoutput
0
TMP92CF29A
PF0D
PF0F
Output port
PF0C
PF0
0
1
−
0
0
−
0
2009-06-11
0
−
0
1