TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 712

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

LCDMODE0
LCDCTL0
Symbol
LCDDVM0
LCDDVM1
LCDSIZE
MODE1
LCD
(6) LCD controller (1/4)
LCD
mode0
register
LCD
mode1
register
LCD
divide
frame0
register
LCD
divide
frame1
register
LCD size
register
LCD
control0
register
Name
Address
0280H
0281H
0283H
0288H
0284H
0285H
000: Normal
001: Horizontal flip
010: Vertical flip
RAMTYPE1 RAMTYPE0
Common setting
0000: Reserved
0001: 64
0010: 96
0011: 120
0100: 128
0101: 160
0110: 200
0111: 240
PIP
function
0: Disable
1: Enable
Display RAM
00: Internal RAM
01: External SRAM
10: SDRAM
11: Reserved
Data rotation function
(Supported for 64K-color: 16bps only)
011: Horizontal & vertical flip
COM3
FMP7
LDC2
FMP3
PIPE
0
0
7
0
0
0
0
Segment
Data
0: Normal
1: Always
output “0”
LCP0 DVM (bits 3-0)
LCP0 DVM (bits 7-4)
COM2
FMP6
FMP2
LDC1
ALL0
0
0
6
0
0
0
0
100: 90-degree
101: Reserved
110: Reserved
111: Reserved
92CF29A-710
R/W
R/W
1000: 320
1001: 480
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
FR divide
setting
0: Disable
1: Enable
LD bus transfer speed Mode setting
SCPW2= 0
00: 2-clock
01: 4-clock
10: 8-clock
11: 16-clock
SCPW2= 1
00: 6-clock
01: 12-clock
10: 24-clock
11: 48-clock
FRMON
SCPW1
COM1
FMP1
FMP5
LDC0
0
0
5
1
0
0
0
R/W
LD bus
Inversion
0: Normal
1: Inversion
Always
write “0”
SCPW0
LDINV
COM0
FMP0
FMP4
0
4
0
1
0
0
−
0
R/W
R/W
R/W
0000: Reserved
0001: SR (mono)
0010: SR (4Gray)
0011: Reserved
0100: SR (16Gray)
0101: SR (64Gray)
0110: STN (256 color)
0111: STN
Segment setting
0000: Reserved
0001: 64
0010: 128
0011: 160
0100: 240
0101: 320
0110: 480
Auto bus
inversion
0: Disable
1: enable
(Valid only
for TFT)
AUTOINV INTMODE FREDGE
0111: 640
MODE3
FML3
FML7
SEG3
0
0
3
0
0
0
(4096 color)
Interrupt
selection
0:LLOAD
1:LVSYNC
LHSYNC DVM (bits 3-0)
FR signal
LCP0/Line
selection
0:Line
1:LCP0
LHSYNC DVM (bit 7-4)
MODE2
FML2
FML6
SEG2
DLS
0
0
0
2
0
0
0
R/W
1000: STN (64k color)
1001: Reserved
1010: TFT (256 color)
1011: TFT (4096 color)
1100: TFT (64k color)
1101: Reserved
1110: TFT (mono)
1111: Reserved
FR edge
0: LHSYNC
front edge
1:LHSYNC
back edge
1000: Reserved
1001: Reserved
1010: Reserved
1011: Reserved
1100: Reserved
1101: Reserved
1110: Reserved
1111: Reserved
LCP0
0: Always
output
1: At valid
data only
LLOAD
0: At
setting in
register
1: At valid
data only
width
LCP0OC
MODE1
FML1
FML5
SEG1
TMP92CF29A
W
R/W
0
0
0
1
0
0
0
2009-06-11
LCDC
operation
0: Stop
1: Start
LD bus
transfer
speed
0: normal
1: 1/3
SCPW2
START
MODE0
FML0
FML4
SEG0
W
0
0
0
0
0
0
0