TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 750

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

SC1MOD0
SC1MOD1
Symbol
BR1ADD
SC1BUF
SIR1CR
SC1CR
BR1CR
UART/Serial channels (2/2)
Serial
channel 1
buffer
register
Serial
channel 1
control
register
Serial
channel 1
mode 0
register
Serial
channel 1
baud rate
control
register
Serial
channel 1
K setting
register
Serial
channel 1
mode 1
register
IrDA 1
control
register
Name
Address
(Prohibit
(Prohibit
120AH
120BH
120CH
120DH
120FH
1208H
RMW)
1209H
RMW)
Received
data bit8
Transfer
data bit 8
Always
write “0”.
IDLE2
0: Stop
1: Run
Select
transmit
pulse
width
0: 3/16
1: 1/16
Undefined
PLSEL
I2S1
R/W
RB8
RB7
TB8
TB7
0
−
0
0
0
7
R
0: CTS
1: CTS
(16 − K) /16
division
0: Disable
1: Enable
Duplex
0: Half
1: Full
Receive
data
0:“H” pulse
1: “L” pulse
BR1ADDE BR1CK1
Parity
0: Odd
1: Even
disable
enable
FDPX1
RXSEL
EVEN
CTSE
R/W
RB6
TB6
0
0
0
0
6
0
92CF29A-748
R/W
Parity
addition
0: Disable
1: Enable
Receive
function
0:Receive
1:Receive
00: φ T0
01: φ T2
10: φ T8
11: φ T32
Transmit
0: Disable
1: Enable
disable
enable
TXEN
RXE
RB5
TB5
PE
5
0
0
0
0
R (Receive) /W (Transmission)
Wake up
0: Disable
1: Enable
Receive
0: Disable
1: Enable
BR1CK0
Overrun
OERR
RXEN
RB4
TB4
WU
R (Cleared to 0 when read)
4
0
0
0
0
Undefined
R/W
R/W
R/W
00: I/O interface Mode
01: 7-bit UART Mode
10: 8-bit UART Mode
11: 9-bit UART Mode
Select receive pulse width
Set the valid SIRRxD pulse width for equal or
more than
2x × (setting value + 1) + 100ns
Can be set: 1~14
Can not be set: 0, 15
SIR1WD3 SIR1WD2 SIR1WD1 SIR1WD0
1: Error
BR1S3
BR1K3
PERR
Parity
RB3
SM1
TB3
3
0
0
0
0
0
Sets frequency divisor “K” (1~F)
Divided frequency “N” setting
Framing
BR1S2
BR1K2
FERR
SM0
RB2
TB2
2
0
0
0
0
0
R/W
0~F
0: SCLK1 ↑
1: SCLK1 ↓
00: TA0TRG
01: Baud rate generator
10: Internal clock f
11: External clock
SCLKS
(SCLK1 input)
BR1S1
BR1K1
RB1
SC1
TB1
TMP92CF29A
1
0
0
0
0
0
2009-06-11
R/W
0:baud rate
1: SCLK1
generator
pin input
BR1S0
BR1K0
RB0
SC0
TB0
IOC
0
0
0
0
0
0
IO