TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 559

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

External SRAM
Internal RAM
External SDRAM
Display RAM
(6) LD Bus
Note: When SDRAM is used, additional 9 clocks are needed as overhead time for reading each common (line) data.
Note: When SDRAM is used, overhead time is added as follows:
The output format can be selected according to the input method of the LCD driver to be
used.
RAM and transfers it to the external LCD driver via the data bus pin dedicated to the LCD.
Thus, the LCDC automatically issues a bus request to the CPU (to stop CPU operation)
when it needs to read data from the display RAM. The bus occupancy rate of the LCDC
varies depending on the display mode and the speed at which data is read from the display
RAM.
is defined as t
The data to be transferred to the LCD driver is output via a dedicated bus (LD15 to LD0).
The LCDC reads data of the size corresponding to the specified LCD size from the display
The time the CPU stops operating while data for one common (line) is being transferred
When internal RAM is used, additional 1 clock is needed as overhead time for reading each common (line)
data. Additional 1 clock of overhead time is also needed when a change of blocks occur in the internal RAM
even if the common (line) remains the same.
t
The bus occupancy rate indicates the proportion of the one common (line) update time t
and is calculated by the following equation:
CPU bus occupancy rate = t
STOP
t
SegNum
K
STOP
[s] = (SegNum × K / 8) × t
= (SegNum × K / 8) × t
STOP,
: Number of bits needed for displaying one pixel
Monochrome display
4-grayscale display
16-grayscale display
256-color display
4096-color display
65536-color display
Bus Width
which is represented by the following equation:
16-bit
32-bit
16-bit
: Number of display segments
STOP
LRD
[s] / LHSYNC [s: period]
92CF29A-557
+ ((1 / f
Valid Data Read Time
LRD
(2 + number of waits) / 2
(f
SYS
SYS
) × 8)
clocks/bytes)
**1/4
*1/2
K=16
K=1
K=2
K=4
K=8
K=12
Valid Data Read Time
at f
t
LRD
SYS
LP
(ns/bytes)
**4.16
*8.33
occupied by t
16.6
= 60 MHz
TMP92CF29A
2009-06-11
STOP