TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 487

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

3.17.11 Notice and Restrictions
1. When using the USB device controller in the TMP92CF29A, a crystal oscillator is
2. Precaution for using the USB dual packet mode in the TMP92CF29A
packets A and B are active, if the respective PKT_ACTIVE bits are read sequentially,
the state of each bit may change between each read. If this happens, the packets may
not be processed in proper order.
captured and saved in another location such as RAM by using an interrupt request.
Then, use this saved information to perform branch processing.
B) to be controlled alternately by hardware.
packets to determine which packet should be processed first. At this time, the
following precaution is required.
separately for packets A and B. The CPU is required to check the respective
PKT_ACTIVE bits to determine which packet was accessed first and then to know the
number of data in this packet. The packet with its PKT_ACTIVE bit set to “1” is the
packet which was received first.
recommended (USB standard ≤ 10 MHz±2500ppm). In this case, a maximum of 3
stages of external hub can be due to the precision of this USB device controller and
the internal clock. If USB compliance (USB logo) is needed, the 5 stages connection is
needed for external hub. And it is needed that input 48MHz clock from X1USB pin
(USB standard ≤ ±2500ppm.)
In determining whether only packet A is active, only packet B is active, or both
Therefore, the PKT_ACTIVE bit information in the EPx_SIZE register should be
In the dual packet mode, each FIFO is divided into two independent packets (A and
When reading data from a receive FIFO, it is necessary to check the state of the two
The EPx_SIZE register that indicates the presence of valid data is provided
92CF29A-485
TMP92CF29A
2009-06-11