TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 160

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

PLDR
(0095H)
PL
(0054H)
PLCR
(0056H)
PLFC
(0057H)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for the registers PLCR, PLFC.
Note2: When PL is used as LD7 to LD0, set applicable PLnC to”1”.
PL7C
PL7F
PL7D
PL7
<PLnF>
7
7
0
−
7
0
−
7
1
−
0
−
0
1
<PLnC>
PL6C
PL6D
PL6F
PL6
6
6
0
6
0
0
−
−
−
6
1
−
Figure 3.8.37 Register for Port L
Input port
Input/Output buffer drive register for standby mode
0
Port L function register
Port L control register
PL5C
0: Port 1: Data bus for LCDC (LD7 toLD0)
PL5F
PL5D
PL5
Port L drive register
5
5
5
0
−
5
1
−
0
−
0
−
92CF29A-158
Port L register
LDn
Output port
0: Input 1: Output
PL4C
PL4F
PL4D
PL4
1
4
4
4
0
−
4
1
−
0
−
0
−
R/W
R/W
W
W
PL3C
PL3F
PL3D
PL3
3
3
3
0
−
0
−
0
−
3
1
−
PL2C
PL2F
PL2D
PL2
2
2
2
0
−
0
−
0
−
2
1
−
PL1C
PL1F
PL1
PL1D
1
1
1
0
−
0
−
0
−
1
1
−
TMP92CF29A
PL0C
PL0F
PL0D
PL0
0
0
0
0
−
0
0
−
0
−
1
−
2009-06-11