TMP92xy29FG Toshiba, TMP92xy29FG Datasheet - Page 171

• Manufacturer Part Number: TMP92xy29FG
• Manufacturer: Toshiba

Specifications of TMP92xy29FG

• Package: QFP176
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 98
• Power Supply Voltage(v): 3.0 to 3.6

PPFC2
(0061H)
PP3 setting (<PP1F2> = 0)
<PP3F>
<PP3C>
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: When setting <PP3F2, PP2F2, PP1F2> = "1", PP3 ~ PP5 pins are set to SIO0 or SIO1 functions regardless
Note2: A read-modify-write operation cannot be performed for the registers PPCR, PPFC.
Note3: When setting PP5, PP4, PP3 pins to INT7,INT6,INT5 input, set PPDR<PP5D:3D> to “0000” (prohibit input),
INT5 input
Input port
0
PPCR, PPFC setting. PP3 is set to TXD, PP4 is set to RXD. PP5 is set to SCLK input or CTS input when
<PP5C> = 0. PP5 is set to SCLK output when <PP5C> = 1.
and when driving PP5,PP4,PP3 pins to “0”, execute HALT instruction. This setting generates INT7, INT6, and
INT5 inside. If don’t using external interrupt in HALT condition, set like an interrupt don’t generated.
Output port
7
TA7OUT
output
1
PP5
SCLK
output
0: SCLK1
1: SCLK0
SIO1
SCLK,
0: PP5
1: P92
CTS input
PP6F2
6
0
−
PP4 setting (<PP2F2> = 0)
Figure 3.8.48 Register for Port P
<PP4F>
<PP4C>
0
1
SIO1
RXD
selection
0: PP4
1: P91
Port P Function register 2
PP5F2
5
0
−
92CF29A-169
INT5 input
Input port
W
0
PP3
selection
0: TXD1
1: TXD0
PP4F2
4
0
−
Output port
TB0IN0
input
PP5
selection
0: Others
1: SCLK,
1
PP3F2
put or
SCLK
output
CTS in
3
0
−
<PP5F>
PP5 setting (<PP3F2> = 0)
PP4
selection
0: Others
1: RXD
<PP5C>
PP2F2
input
0
1
−
2
0
INT7 input
Input port
PP3
selection
0: Others
1: TXD
PP1F2
output
0
1
0
−
Output port
TB1IN0
PP3
selection
0: CMOS
1: Open
TMP92CF29A
input
PP0F2
-drain
1
0
0
−
2009-06-11